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features ? 5 smart card interfaces ? compliance with iso 7816, emv2000, gie-cb and gsm standards ? direct connection to the smart cards logic level shifters short circuit current limitation 4kv+ esd protection (mil/std 883 class 3) ? 1 or 2 master smart card interfaces synchronous card support (with c4 and c8 contacts) card detection and automatic de-activation sequence on card extraction ? 1 to 4 sam/sim cards (15 to 30ma each) ? programmable voltage for each smart card class a: 5v 0.4v at 60 ma (0.25v at 65 ma with vc c= 5v10%) class b: 3v 0.2v at 60 ma class c: 1.8v 0.14v at 40ma ? low ripple noise: < 200 mv ? programmable activation sequence ? automatic de-activation on card power-fail or over -current and system power-fail ? card clock stop high or low for card power-down mo des ? versatile host interface ? two wire interface (twi) link at 400kbit/s programmable address allow up to 4 at83c26 on the b us ? programmable interrupt output ? reset output includes ? power-on reset (por) ? power-fail detector (pfd) ? extended voltage operation: 3 to 5.5v ? low power consumption ? 5 ma maximum operating current (without smart card ) ? 150 ma maximum in-rush current (each dc/dc) ? 30 a typical power-down current (without smart card) ? 4 to 48 mhz clock input ? system clock derived from the external clock input ? industrial temperature range: -40 to +85 c ? packages: qfn48, vqfp48 description the at83c26 is a smart card reader interface ic for smart card reader/writer applica- tions such as eft/pos terminals and set top boxes. it enables the management of any type of smart card from any kind of host. up to 4 at83c26 can be connected in parallel thanks to the programmable twi address. its high efficiency dc/dc converters and low quiesc ent current in stand-by mode make it particularly suited to low power and portab le applications. the reduced bill of material allows to lower significantly the system s ize and cost. a sophisticated protec- tion system guarantees timely and controlled shutdo wn upon error conditions. multiple smart card reader interface with power management at83c26 7511d?scr?02/07
2 7511d?scr?02/07 at83c26 acronyms twi: two wire interface por: power on reset pfd: power fail detect art: automatic reset transition atr: answer to reset block diagram note: 1. crst3/cc82 are on the same pin. cio3/cc42 ar e on the same pin. if complete smart card 2 interface is used, sam/sim3 isn?t available. respec tively, if sam/sim3 is used, complete smart card 2 isn?t available. int crst1 cpres1 cvcc1 lia reset voltage supervisor por/pfd twi controller dc/dc converter a analog drivers scl sda main control & logic unit cvss1 clock circuit cclk cclk1 clock controller timer 16 bits a2/ck, a1/rst clk cvccin1 cio1 cc41 cc81 crst2 cpres2 cclk2 cio2 smart card 1 smart card 2 crst3, see (1) cclk3 cio3, see (1) crst4 cclk4 cio4 crst5 cclk5 cio5 sam/sim 1 sam/sim 2 sam/sim 3 i/0 selection i/o1 i/o2 aux1 aux2 cvcc3 dc/dc converter b cvcc5 cvcc4 ldo ldo ldo cvcc2 ldo lib cvssb cvccb vcc vss cc82, see (1) cc42, see (1) cvccinb sc1 sc2 sc3 sc4 sc5 evcc bypass
3 7511d?scr?02/07 at83c26 pin description pinout (top view) vqfp48 pinout qfn48 pinout 1 23 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 top view vqfp 48 cvcc3 cvcc4 crst4 cclk4 cio4 cvcc5 crst5 cclk5 cio5 crst3/cc82 cclk3 cio3/cc42 cio1 cc81 cpres1 cc41 cclk1 crst1 lia cvccin1 cvcc1 vcc cvss1 cvcc1 cio2 cpres2 cclk2 cvcc2 evcc lib cvssb r eset cvccinb crst2 cvccb cvccb clk i nt io1 io2 aux1 aux2 a1/rst a2/ck vss scl sda bypass 1 23 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 top view qfn 48 cio2 cpres2 cvcc3 cvcc4 crst4 cclk4 cio4 cvcc5 crst5 clk i nt cio1 cc81 cpres1 cc41 cclk1 crst1 cclk2 cvcc2 evcc cclk5 cio5 io1 io2 aux1 aux2 a1/rst a2/ck lia cvccin1 cvcc1 crst3/cc82 cclk3 cio3/cc42 lib cvssb vss vcc r eset scl sda cvccinb bypass crst2 cvccb cvss1 cvcc1 cvccb
4 7511d?scr?02/07 at83c26 signals table 1. ports description vqfp48 or qfn48 pin number pad name pad internal power supply pad type description 1 cvcc3 pwr vcc pin for sc3 interface. 2 crst3/cc82 cvcc3 i/o pull up see sc2_cfg1 register: if sc2_full bit = 0, crst pin for sc3 interface. if sc2_full bit = 1, cc8 pin for sc2 interface. 3 cclk3 cvcc3 o cclk pin for sc3 interface. 4 cio3/cc42 cvcc3 i/o pull up see sc2_cfg1 register: if sc2_full bit = 0, cio pin for sc3 interface. if sc2_full bit = 1, cc4 pin for sc2 interface. 5 cvcc4 pwr vcc pin for sc4 interface. 6 crst4 cvcc4 o rst pin for sc4 interface. 7 cclk4 cvcc4 o cclk pin for sc4 interface. 8 cio4 cvcc4 i/o pull up cio pin for sc4 interface. 9 cio5 cvcc5 i/o pull up cio pin for sc5 interface. 10 cclk5 cvcc5 o cclk pin for sc5 interface. 11 crst5 cvcc5 o rst pin for sc5 interface. 12 cvcc5 pwr vcc pin for sc5 interface. 13 cc81 cvcc1 i/o pull up cc8 pin for sc1 interface. 14 cc41 cvcc1 i/o pull up cc4 pin for sc1 interface. 15 cio1 cvcc1 i/o pull up cio pin for sc1 interface. 16 cclk1 cvcc1 o cclk pin for sc1 interface. 17 crst1 cvcc1 o rst pin for sc1 interface. 18 cvccin1 pwr this pin must be connected to cvcc1 pin s next to the package. 19 cpres1 vcc i pull up card presence for sc1 interface. an internal pull up to vcc can be activated in the pad if necessary using pullup1 bit in sc1_cfg1 register (activated by defa ult). 20 cvcc1 pwr vcc pin for sc1 interface. the two cvcc1 pins are connected together near the package. only one wire goes to the smart card connector. the reason o f two cvcc1 pins is to reduce noise. 21 cvcc1 pwr vcc pin for sc1 interface.
5 7511d?scr?02/07 at83c26 22 lia pwr dc/dca input. lia must be tied to vcc pin through an external coi l (typically 10h) and provides the current for the charge pump of the dc/ dca converter. it may be directly connected to vcc if the step-up converter is not used (see steprega bit in sc1_cfg4 register and see mini mum vcc values in table 50.for class a and table 51. for cl ass b) 23 cvss1 gnd dc/dca input. this pin must be directly connected to the vss of p ower supply. 24 vcc pwr vcc is used to power the internal voltage r egulators and i/o buffers. 25 vss gnd ground. 26 bypass vcc i a high level on this pin activates a low power cons umption mode with internal regulator bypassed. 27 sda vcc i/o open drain micro controller interface function: twi serial dat a. an external pull up must be connected on sda pin (4 .7kohms). 28 scl vcc i/o open drain micro controller interface function: twi clock. an external pull up must be connected on scl pin (4 .7kohms). 29 io2 evcc i/o pull up the behavior of this pin depends on iosel[3/0] bits values (see io_select register). 30 io1 evcc i/o pull up the behavior of this pin depends on iosel[3/0] bits values (see io_select register). 31 aux2 evcc i/o pull up the behavior of this pin depends on iosel[3/0] bits values (see io_select register). 32 aux1 evcc i/o pull up the behavior of this pin depends on iosel[3/0] bits values (see io_select register). 33 a1/rst evcc i the twi address depends on the value present on thi s pin at reset. if crst transparent mode is selected, the a1/rst si gnal is connected to crst1 or crst2 pins (see crst_sel1 and crst_sel2 bi ts respectively in sc1_cfg4 and sc2_cfg2 registers). 34 a2/ck evcc i the twi address depends on the value present on thi s pin at reset. if cclkn transparent mode is selected, the a2/ck si gnal is connected to cclkn pins (with n=1 to 5). see cksn[2:0] bits respectively in sc1_cfg1, sc2_cf g2, sc3_cfg2, sc4_cfg2, sc5_cfg2 registers. 35 clk evcc i master clock. 36 i nt vcc o open drain interruption status. an internal pull up to vcc can be activated in the pin if necessary using int_pullup bit in sc1_cfg4 (deactivated by default) . 37 evcc pwr extra supply voltage (micro controller power supply ). evcc is used to supply the internal level shifters of host interface pins. evcc is connected to the host power supply. evcc voltage can be directly connected to vcc if th e host power supply and the at83c26 power supply is the same. table 1. ports description (continued) vqfp48 or qfn48 pin number pad name pad internal power supply pad type description
6 7511d?scr?02/07 at83c26 note: the esd limit is 4kv for smart card pins and 2 kv for others. 38 cvssb gnd dc/dcb input. this pin must be directly connected to the vss of p ower supply. 39 lib pwr dc/dcb input. lib must be tied to vcc pin through an external coi l (typically 10h) and provides the current for the charge pump of the dc/ dcb converter. it may be directly connected to vcc if the step-up converter is not used (see stepregb bit in dcdcb register and see minimum vcc values in table 53.for class a and table 54. for class b) 40 cvccb pwr dc/dcb output. the two cvccb pins are connected together near the package. cvccb pin is only used for dc/dcb voltage measurements.th e reason of two cvccb pins is to reduce noise. 41 cvccb pwr dc/dcb output. 42 r eset vcc i/o open drain micro controller interface function: reset signal. ? power on reset ? a low level on this pin keeps the at83c26 under re set even if applied on power-on. it also resets the at83c26 if applied when the at83c26 is running. ? asserting r eset 43 cpres2 vcc i pull up card presence for sc2 interface. an internal pull to vcc can be activated in the pad if necessary using pullup2 bit in sc2_cfg1 register (activated by defa ult). 44 cvccinb pwr this pin must be connected to cvccb pin s next to the package. 45 cvcc2 pwr vcc pin for sc2 interface. 46 crst2 cvcc2 o crst pin for sc2 interface. 47 cclk2 cvcc2 o cclk pin for sc2 interface. 48 cio2 cvcc2 i/o pull up cio pin for sc2 interface. table 1. ports description (continued) vqfp48 or qfn48 pin number pad name pad internal power supply pad type description
7 7511d?scr?02/07 at83c26 pad type description to simplify the understanding of figure 1. to figur e 8., a shortcut is possible by replacing the weak transistor by a 100k ohms pull-up resistor, th e medium transistor by a 10k ohms pull-up resistor and the strong transistor by a 1k ohms pull-up resistor. input/output with pull-up configuration (io1, io2, aux1, aux2) this output type can be used as both an input and o utput without the need to reconfigure the port. this is possible because when the port output s a logic high, it is weakly driven, allowing an external device to pull the pin low. when the port outputs a logic low state, it is driven strongly and able to sink a fairly large current. figure 1. input/output with pull-up configuration input/output with pull-up configuration (cion with n = 1, 2, 3, 4, 5) and (cc4n, cc8n with n = 1, 2) figure 2. input/output with pull-up configuration 2 dcclk input pin strong keep n p p clock delay port latch data data pmos nmos 2 dcclk input pin strong medium n p p clock delay port latch data data pmos nmos slew control with cion_slew_ctrl bits (n= 1 to 5)
8 7511d?scr?02/07 at83c26 input/output with open drain configuration (sda, sc l, r eset ) figure 3. input/output with open drain configuration output configuration (cclkn with n = 1, 2, 3, 4, 5) figure 4. output configuration output configuration (crstn with n = 1, 2, 3, 4, 5) figure 5. output configuration input pin n port latch data data nmos pin strong n p port latch data pmos nmos slew control with cion_slew_ctrl bits pin strong n p port latch data pmos nmos
9 7511d?scr?02/07 at83c26 open drain output with programmable pull-up configu ration (int ) figure 6. open drain output with programmable pull-up input configuration (a1, a2, clk, bypass) figure 7. input input with programmable pull-up configuration (cpre s1, cpres2) figure 8. input with programmable pull-up pin weak n p port latch data nmos int_pullup bit input pin data input data pin weak p int_pullup bit
10 7511d?scr?02/07 at83c26 operational modes twi bus control the atmel two-wire interface (twi) interconnects co mponents on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. the twi-bus interface can be used: ? to configure the at83c26 ? to select interface ? to select the operating mode of the card: 1.8v, 3v or 5v ? to configure the automatic activation sequence ? to start or stop sessions (activation and de-activ ation sequences) ? to initiate a warm reset ? to control the clock to the card in active mode ? to control the clock to the card in stand-by mode (stop low, stop high or running) ? to enter or leave the card stand-by or power-down modes ? to select the interface (connection to the host i/ o/c4/c8) ? to request the status (card present or not, over-c urrent and out of range supply voltage occurrence) ? to drive and monitor the card contacts by software ? to accurately measure the atr delay when automatic activation is used ? re-use the at83c24 command set for the first dc/dc and smart card interface with the following changes: ?cks extended to config2[0:3], cks=8 selects clk/3 and cks>8 is reserved ?the slave address byte for twi write commands is 0 100 a 2 a 1 10 and 0100 a 2 a 1 11 for twi read commands twi commands frame structure the structure of the twi bus data frames is made of one or a series of write and read com- mands completed by stop. write commands to the at83c26 have the structure: address byte + command byte + data byte(s) read commands to the at83c26 have the structure: address byte + data byte(s) the address byte is sampled on a2/ck and a1/rst after each reset (hard/soft/general call) but a2/ck, a1/rst can be used for transparent mode after the reset.
11 7511d?scr?02/07 at83c26 figure 1. data transfer on twi bus address byte the first byte to send to the device is the address byte. the device controls if the hardware address (a2/ck, a1/rst pins on reset) corresponds t o the address given in the address byte (a2, a1 bits). if the level is not stable on a2/ck pin at reset, t he user has to manage the possible address taken by the device. figure 2. address byte up to 4 devices can be connected on the same twi bu s. each device is configured with a differ- ent combination on a2/ck, a1/rst pins. the address byte of each device for read/write operations are listed below. sda scl start condition stop condition 1 2 3 4 5 6 7 8 9 acknowledgement from slave address byte command and/or data table 2. address byte values a2 (a2/ck pin) a1 (a1/rst pin) address byte for read command address byte for write command 0 0 0x43 0x42 0 1 0x47 0x46 1 0 0x4b 0x4a 1 1 0x4f 0x4e b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 a2 a1 1 r/w slave address on 7 bits 1 for read command 0 for write command
12 7511d?scr?02/07 at83c26 r eset pin the twi address byte is sampled on a2/ck and a1/rst after a rising edge on r eset pin. the delay between the rising edge and the sampling of a2/ck and a1/rst is t1. the value for t1 is 22 clk period. the minimum value for t2 is 40 clk period. during t he t2 time, the twi bus is not ready to receive a command. the clk period depends on the frequency of the sign al on clk pin. the r eset pin is an i/o with open drain. the host io pin con nected to r eset must be an i/o open drain (with external pull-up) or an i/o open d rain with internal pull up. figure 3. timings after reset bypass pin a high level on this pin activates a low power cons umption mode. at reset, the level on this pin must be fixed (vss or vcc). before to set bypass pin, shutdowna and shutdownb b its must be set. if shutdowna bit is set, dcdca is switched off. if shutdownb bit is set, dcdcb is switched off. if shutdowna and shutdownb bits are set, the regula tor is switched off. if bypass pin is at a high level, the bandgaps are switched off. smart card interfaces the at83c26 enables the management of up to 5 smart card interfaces. due to shared ios between sc2 and sc3, the user should choose between a full sc2 interface (with cc4 and cc8) or sc3 interface. the sc2_full bit in sc2_cfg1 register is used to se lect the sc2/sc3 interfaces configuration. sda address byte r eset sampling of twi address t1 t2
13 7511d?scr?02/07 at83c26 table 3. sc2 and sc3 shared ios dcdc converters the dc/dc a converter is used to provide smart card voltage for the sc1 interface (cvcc1). the dc/dc b converter is used to provide smart card voltage for the scn interfaces (n=2, 3, 4, 5). dc/dc converters need a clock of 4mhz (see section ?clock controller?). two internal oscilla- tors (one for each converter) provide the dc/dc clo cks. the dc/dcb output is connected on 4 ldo regulators (low drop output) to generate cvccn voltage (n=2, 3, 4, 5). clock controller the clock controller outputs six clocks: 1. five clocks for cclk1, cclk2, cclk3, cclk4 and cc lk5. four different sources can be used: clk pin, dcclk signal, cardckn bit (n=1, 2 , 3, 4, 5) or a2/ck. 2. a dcclk clock used for pads and deactivation sequ ence. clock controller for scn (n=1, 2, 3, 4, 5) the transparent mode with a2/ck pin is available on scn interface. the cksn[2:0] register is used to select this transparent mode between a2/ck and cclkn. the bit ckstopn must be cleared to have cclkn running according to cksn[2:0 ]. pin name sc2_full = 1 sc3 interface not available sc2_full = 0 sc2 without cc4and cc8 + sc3 interface cpres2 crst2 cio2 cclk2 crst3/cc82 cio3/cc42 cclk3 cpres2 crst2 cio2 cclk2 cc82 cc42 unused cpres2 crst2 cio2 cclk2 crst3 cio3 cclk3
14 7511d?scr?02/07 at83c26 figure 4. clock block diagram with software activation crst controller crstn for scn interface (n=1, 2) the crstn output pin is driven by the cardrstn bit value or by a1/rst pin. three modes are available: ? if the artn bit is reset, crstn pin is driven by c ardrstn bit. ? if the artn bit is set, crstn pin is controlled an d follows the ?automatic reset transition? (see activation sequence page 25). ? a transparent mode with a1/rst pin. figure 5. crstn block diagram dck[2:0] cksn[2:0] clk a2/ck cclkn dc/dca 0 1 ckstopn bit cardckn bit internal oscillators and b dcclk crstn 0 1 artn bit cardrstn bit cardrstn bit tb delay a1/rst 0 1 crst_seln bit
15 7511d?scr?02/07 at83c26 crstn for scn interface (n= 3, 4, 5) the crstn output pin is driven by the cardrstn bit value (see scn_cfg2 register). two modes are available: ? if the artn bit is reset, crstn pin is driven by c ardrstn bit. ? if the artn bit is set, crstn pin is controlled an d follows the ?automatic reset transition? (see activation sequence page 25). figure 6. crstn block diagram if sc2_full=1, the sc3 interface is not available. cio, cc4, cc8 controller cio1, cc41, cc81 controller for sc1 interface the cio1, cc41, cc81 output pins are driven respect ively by cardio1, cardc41, cardc81 bits values or by i/o1, i/o2, aux1or aux2 signals. this selection depends of the iodis1 bit value (sc1_interface register) and of iosel[3:0] bi ts value (io_select register). figure 7. cio1, cc41, cc81 block diagram if iodis1 is set, the cardio1 bit value is output o n cio1.the input selected by iosel for cio1 is in high impedance state. cc41 and cc81 have the same behavior. if iodis1 is reset, data are bidirectional between the i/o1, i/o2, aux1, aux2 pins (see io_select register) and cio1, cc41, cc81 pins. crstn 0 1 artn bit cardrstn bit cardrstn bit tb delay cio1 0 1 0 1 cardio1 bit cc41 cc81 0 1 cardc81 bit iodis1 bit cardc41 bit io1 io2 aux2 aux1 iosel[3:0] hiz control multiplex
16 7511d?scr?02/07 at83c26 cio2, cc42, cc82 controller for sc2 interface figure 8. cio2, cc42, cc82 block diagram the sc2_full bit must be set to use cc42 and cc82. cion controller for scn interface (n=3, 4, 5) the cion output pin is driven by cardion bit values or by i/o1, i/o2, aux1 or aux2 signals. this selection depends of the iodisn bit value. if iodisn is reset, data are bidirectional between the i/o1, i/o2, aux1, aux2 pins (see io_select regi ster) and cion pins. figure 9. cion block diagram cion (n=1 to 5), cc41, cc81, cc42, cc82 transparent mode description two modes are available on cion, cc4n, cc8n signals : ? bit control (a bit controls the output pin) ? transparent mode (io signal and cio are linked aft er level shifter) according to io_select register value and iodisn bi ts values, one of 4 input pins (io1, io2, aux1 or aux2) is linked to the selected output. the idle state is the high level. each signal is bi directional. cio2 0 1 0 1 cardio2 bit cc42 cc82 0 1 cardc82 bit cardc42 bit io1 io2 aux2 aux1 hiz control multiplex iodis2 bit iosel[3:0] cion 0 1 cardion bit iodisn bit io1 io2 aux2 aux1 iosel[3:0] hiz control multiplex
17 7511d?scr?02/07 at83c26 transparent mode arbitration system the first between io and cio to force a low level b ecomes the master. the slave signal is grounded after t1 delay: t1 max = 2* (clk period). figure 10. bidirectional mode the minimum delay for a pulse at 0 or 1 to be detec ted is between 0.5 and 1.5 clk period (depending on arrival time). if io and cio are both grounded, cio becomes the ma ster. the minimum delay to switch of master without elect rical conflict is equal to: t2 min = 4 * (clk period) + 2 * (dcclk period) * (c lk period). if a master switch appears before this minimum dela y, the electrical conflict delay is: t2 = 2 * (dcclk period) * (clk period) figure 11. electrical conflict master master t1 t1 io cio t1 t1 t2 slave slave master master t1 io cio t2 slave slave cio pad becomes output
18 7511d?scr?02/07 at83c26 cclkn and cion (n=1 to 5) slew rate control three registers slew_ctrl_1, slew_ctrl_2 and slew_c trl_3 control the slew rate of the cion and cclkn signals. each signal has 2 contr ol bits. an automatic mode is proposed. the vcardn[1:0] valu e is used to automatically adjust the slew rate. for specific cases, like long wires between at83c26 and smart card connector for example, the user can forced the slew rate. the rising edge and the falling edge are modified w ith the slew rate control for cclkn. only the rising edge is modified on cion with the s lew rate control. see table 63. to table 68. in electrical characteri stics.
19 7511d?scr?02/07 at83c26 card presence detection card presence detection for sc1 interface the card presence signal is connected on the cpres1 pin. the polarity of card presence con- tact is selected with the carddet1 bit (see sc1_cfg 1 register). a programmable filtering is controlled with the cds1[2-0] bits. the internal pull-up on the cpres1 pin can be disco nnected in order to reduce the consump- tion. an external pull-up must be connected to vcc. the pullup1 bit (see sc1_cfg1 register) controls this feature. figure 12. sc1 presence input if the card presence contact is connected to vcc, t he internal pull-up must be disconnected and an external pull-down must be connected to the cpre s1 pin. an interrupt can be generated if a card is inserted or extracted (see section ?interrupts?, page 30). card presence detection for sc2 interface figure 13. sc2 presence input pullup1 bit carddet1 bit = 1 closed = 0 open external pull-up resistor card presence contact = 1 no card if cpres1 = 0 = 0 no card if cpres1 = 1 cardin1 bit = 1 card inserted = 0 no card cpres1 int vcc filtering cds1[2-0] vcc vss int_pullup bit = 1 closed = 0 open vcc external pull-down resistor card presence contact vcc vss pullup2 bit carddet2 bit = 1 closed = 0 open external pull-up resistor card presence contact = 1 no card if cpres2 = 0 = 0 no card if cpres2 = 1 cardin2 bit = 1 card inserted = 0 no card cpres2 int vcc filtering cds2[2-0] vcc vss int_pullup bit = 1 closed = 0 open vcc external pull-down resistor card presence contact vcc vss itdis2 bit = 0 closed = 1 open
20 7511d?scr?02/07 at83c26 dc/dc converters dc/dc a converter the dc/dc a converter is controlled by vcard1[1:0], shutdowna, iccadja, steprega, vcard_ok1 and demboosta[1:0] bits. the dc/dc a converter cannot be switched on while t he cpres1 pin remains inactive. if cpres1 pin becomes inactive while the dc/dc a conve rter is operating an automatic shut down sequence of the dc/dc a converter is initiated by the electronics. a write operation in vcard1[1:0] (0x01, 0x02, 0x03) starts the dc/dc. when the output voltage remains within the voltage range specified by vcard 1[1:0], the vcard_ok1 bit is set. after a deactivation sequence (card extraction, dc/ dc output voltage out of range, shut- downa bit =1...) the dc/dc a converter is automatic ally stopped. it is mandatory to switch off the dc/dc a converter before entering in power-down mode. the dc/dc a converter can work in two different mod es which are selected by steprega bit: ? pump mode (steprega = 0): an external inductance o f 10 h must be connected between pins lia and vcc. vcc can be higher or lowe r than cvcc1. ? regulator mode (steprega = 1): no external inducta nce is required but vcc must be always higher than cvcc+0.3v. the current drawn from power supply by the dc/dc a converter is controlled during the startup phase in order to avoid high transient current main ly in pump mode which could cause the power supply voltage to drop dramatically. this con trol is done by means of bits dem- boosta[1:0], which increases progressively the star tup current level. the dc/dca sensitivity to any overflow current can be modified (20%) by using the iccadja bit (sc1_cfg3 register). initialization procedure for dc/dc a converter the initialization procedure is described in flow c hart: ? select the cvcc1 level by means of bits vcard1[1:0 ] in sc1_cfg0 register, ? set bits demboosta[1:0] in sc1_cfg4 register follo wing the current level control wanted. ? monitor vcard_ok1 bit in sc1_status register in or der to know when the dc/dc a converter is ready (cvcc1 voltage has reached the e xpected level) while vcc1 remains higher than 3.6v and startup cur rent lower than 30 ma (depending on the load type), the dc/dc a converter should be ready w ithout having to increment dem- boosta[1:0] bits beyond [0:0] level. if at least on e of the two conditions are not met (vcc < 3.6v or startup current > 30 ma), it will be necess ary to increment the demboosta[1:0] bits until the dc/dc converter is ready. increment of demboosta[1:0] bits increases at the s ame time the current overflow level in the same proportion as the startup current. so once the dc/dc converter is ready it advised to dec- rement the demboosta[1:0] bits to restore the overf low current to its normal or desired value.
21 7511d?scr?02/07 at83c26 figure 9. dc/dc a converter initialization procedure dc/dc b converter the dc/dc b converter is controlled by dcdcb regist er. the dc/dc b converter can be switched on even if cp res2 pin remains inactive. a write operation in vdcb[1:0] (0x01, 0x02, 0x03) s tarts the dc/dc. when the output voltage remains within the voltage range specified by vdcb_ ok[1:0], the vdcb_ok bit is set. the dc/dc b converter can work in two different mod es which are selected by stepregb: ? pump mode (stepregb = 0): an external inductance o f 10 h must be connected between pins lib and vcc. vcc can be higher or lowe r than selected voltage. ? regulator mode (stepregb = 1): no external inducta nce is required but vcc must be always higher than selected voltage+0.3v. the current drawn from power supply by the dc/dc b converter is controlled during the startup phase in order to avoid high transient current main ly in pump mode which could cause the power supply voltage to drop dramatically. this con trol is done by means of bits dem- boostb[1:0], which increases progressively the star tup current level. demboosta[1:0]=[0:0] vcard_ok1=1 set time-out to 3 ms time-out expired demboosta[1:0] is at maximum? dc/dc a converter initialization failure end end decrement demboosta[1:0] to adjust the current overflow increment demboosta[1:0]
22 7511d?scr?02/07 at83c26 the dc/dcb sensitivity to any overflow current can be modified (20%) by using the iccadjb bit (dc/dcb register). initialization procedure for dc/dc b converter the initialization procedure is described in flow c hart: ? select the dc/dc b level by means of bits vdcb[1:0 ] in dcdcb register, ? set bits demboostb[1:0] in interfaceb register fol lowing the current level control wanted. ? monitor vdcb_ok bit in dcdcb register in order to know when the dc/dc b converter is ready figure 10. dc/dc b converter initialization procedure increment of demboostb[1:0] bits increases at the s ame time the current overflow level in the same proportion as the startup current. so once the dc/dc b converter is ready it advised to decrement the demboostb[1:0] bits to restore the ov erflow current to its normal or desired value. demboostb[1:0]=[0:0] vdcb_ok=1 set time-out to 3 ms time-out expired demboostb[1:0] is at maximum? dc/dc b converter initialization failure end end (ready to start ldo) decrement demboostb[1:0] to adjust the current overflow increment demboostb[1:0]
23 7511d?scr?02/07 at83c26 ldo initialization procedure when the dc/dc b voltage rises the selected voltage (vdcb_ok=1), the card voltage selection on cvcc2, cvcc3, cvcc4 or cvcc5 starts the correspo nding ldo. the cvcc2 card voltage must be started in first (if needed). when the vcard_ok2 is set, the cvcc3,cvcc4, cvcc5 card voltage are started one aft er each other (if needed) with the same procedure. the ldo2, ldo3, ldo4 and ldo5 share the dc/dcb outp ut current, for example 75ma max when cvccb is pregrammed to 5v. (see table 62.) the sc2_full bit must be set to use sc2 full interf ace: cio3/cc42 is cc42 and crst3/cc82 is cc82. as the power supply of cio3/cc42 and of crst3/cc82 is cvcc3, when sc2_full=1, cvcc3 = cvcc2. the sc3 interface is disable and ldo 3 receives ldo2 command (vcard3[1:0] = vcard2[1:0]). figure 11. ldon initialization procedure (n = 2, 3, 4, 5) the ldon output voltage must be at 0v before to pro gram 1.8v/3v/5v. init condition: dcdcb started (vdcb_ok = 1) start ldon, write vcardn[1:0] vcard_okn = 1 time-out expired and iplusn=1 ? ldon initialization failure iplusn = 1 set timer 2ms ldon started
24 7511d?scr?02/07 at83c26 activation sequence overview (n=1, 2, 3, 4, 5) the activation sequence on sc1 is only available if a card is detected on cpres1 (cardin1 bit = 1). the activation sequence on sc2 is only available if a card is detected on cpres2 (cardin2 bit = 1). the activation sequence on sc3, sc4, sc5, is only a vailable if dc/dc b is started (vdcb_ok = 1). the scn interface starts the activation sequence af ter a twi write command in vcardn[1:0] bits to program the cvccn voltage. the sc3, sc4, sc5 interfaces (sim/sam interfaces) d on?t have card presence detector. after the dc/dc start, the user application will ch eck the atr to detect if a sim/sam is present in the connector. the automatic reset transition mode (art=1) control s the crst pin and check if the first start bit of the atr respects iso7816 timings. all status bits of an interface (see bits in regist ers with ?this bit is cleared by hardware when this register is read?) must be cleared before to start an activation sequence. software activation for scn interfaces (n=1, 2, 3, 4, 5) with artn bit = 0 the activation sequence is controlled by software u sing twi commands, depending on the cards to support. for iso 7816 cards, the following sequence can be applied: 1. card voltage is set by software to the required v alue (vcardn[1:0] bits). the twi writing command in vcardn[1:0] starts the dc/dc (or ldo). 2. wait of the end of the dc/dc (or ldo) init with a polling on vcard_okn bit or wait for int to go low. when vcard_okn bit is set (by hardware) , cardion bit should be set by software. 3. ckstopn, iodisn are programmed by software. cksto pn bit is reset to have the clock running. iodisn (see io_select for sc2, sc3, sc4, sc5) is reset to enable the transparent mode on cion,cc4n, cc8n. 4. crstn pin is controlled by software using cardrst n bit.
25 7511d?scr?02/07 at83c26 figure 14. software activation without automatic control (artn bit = 0) note: ? it is assumed that initially vcardn[1:0], cardckn, cardion and cardrstn bits are cleared, ckstopn and iodisn are set (those bits are further explained in the registers description) ? the user should check the at83c26 status and possi bly resume the activation sequence if one twi transfer is not acknowledged du ring the activation sequence. software activation for scn (n=1, 2, 3, 4, 5) inter faces and artn bit = 1 the following sequence can be applied: 1. card voltage is set by software to the required v alue (vcardn1:0] bits in scn_cfg0 register). this writing starts the dc/dc c onverter (or ldo). 2. wait of the end of the dc/dc init (or ldo) with a polling on vcard_okn bit or wait for int to go low. when vcard_okn bit is set (by hardware) , cardion bit should be set by software. 3. ckstopn, iodisn are programmed by software. cksto pn bit is reset to have the clock running. iodisn is reset to enable the transp arent mode on cion,cc4n, cc8n. 4. cardrstn bit is set by software. automatic reset transition description: a 16-bit counter starts when cardrstn bit is set. i t counts card clock cycles. the crstn sig- nal is set when the counter reaches the timer_msb a nd timer_lsb value which corresponds to the ?tb? time (figure 15).the counter is reseted when the crstn pin is released and it is stopped at the first start bit of the answer to req uest (atr) on cion pin. the cion pin is not checked during the first 200 cl ock cycles (ta, figure 15). if the atr arrives before the counter reaches timer_msb and timer_lsb values, the activation sequence fails, cvccn crstn cclkn cion 2 4 3 1 atr
26 7511d?scr?02/07 at83c26 the crstn signal is not set and the capture_msb and capture_lsb registers contain the value of the counter at the arrival of the atr. if the atr arrives after the rising edge on crstn p in and before the card clock counter over- flows (65535 clock cycles), the activation sequence completes. the capture_msb and capture_lsb registers contain the value of the coun ter at the arrival of the atr (tc time on figure 15). figure 15. software activation with artn bit = 1 iso 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000 card clock c ycles timer[1-0] reset value is 400. warm reset (n=1, 2, 3, 4, 5) the at83c26 offers a simple and accurate way to con trol the crstn signal during a warm reset. after an activation sequence (cold reset), a warm r eset is started with a low level on crst dur- ing a define delay (between 40000 and 45000 clock c ycles for example). the artn bit, the timer_msb and the timer_lsb are u sed to control crstn. the first step is to load the number of cclk cycles with crstn=0 in timer registers. the warm reset is started by setting art bit (if ar t bit is already set, reset art before). cvccn crstn cclkn tc tb ta cion cardrstn bit set 1 2 3 4
27 7511d?scr?02/07 at83c26 the crst signal will be equal to 0 during the numbe r of clock cycles programmed in timer_msb and timer_lsb. then, the crst signal will be at 1. figure 16. warm reset with artn bit = 1 deactivation sequence overview the deactivation sequence should follows the order defined in iso7816-3 specification. the at83c26 has two deactivation modes: ? standard deactivation mode: this mode is used to s top exchange with smart card when the at83c26 power supply is present. the dcclk signal i s used for deactivation sequence timings. ? emergency deactivation mode: this mode is used whe n the at83c26 power supply is took off. deactivation sequence on scn interface (n=1, 2, 3, 4, 5) the card automatic deactivation is triggered when o ne the following condition occurs: ? icarderr1 bit is set by hardware (sc1) ? vcarderrn bit is set by hardware (or by software) ? insert1 is set and cardin1 is cleared (sc1) ? insert2 is set and cardin2 is cleared (sc2) ? shutdowna bit is set by software (sc1) ? shutdownb bit is set by software (sc2, sc3, sc4, s c5) cvccn crstn cclkn t cion art = 1 t = timer value
28 7511d?scr?02/07 at83c26 ? reset pin going low (sc1, sc2, sc3, sc4, sc5) ? power fail (vpfdp) it is a self-timed sequence which cannot be interru pted when started (see figure 17). each step is separated by a delay based on td equal to 8 peri ods of dcclk, typically 2 to 2.4 s: 1. t0: cardrstn is cleared, shutdowna (for sc1) bit is set. 2. t0 + 5 x td:cardckn is cleared, ckstopn, cardion and iodis are set. 3. t0 + 6 x td: cardion is cleared. 4. t0 + 7 x td: vcardn[1:0] = 00. figure 17. deactivation sequence notes: 1. setting icarderr1 by software does not trig ger a deactivation on sc1. vcarderrn can be used to deactivate the card by software. 2. if cclkn=a2 or a2/2, deactivation follows fig13 w ith 2 timing modifications: t1=5.5*td and t2=0.5*td. 3. td is based on dcclk clock. emergency deactivation sequence on scn interface (n =1, 2, 3, 4, 5) the card emergency automatic deactivation is trigge red when one the following condition occurs: ? software twi reset (sc1, sc2, sc3, sc4, sc5) ? power fail on vcc (sc1, sc2, sc3, sc4, sc5) if the power supply is disconnected, a standard dea ctivation is started when vcc = vpfdp. when vcc is equal to vpfdm, the emergency deactivat ion occurs and eventually ends the standard deactivation. cvcc crst cclk cio, 5 x td td td cc4, cc8 t1 t2
29 7511d?scr?02/07 at83c26 figure 18. power fail detection figure 19. emergency deactivation sequence during an emergency deactivation, the signals fall according to the order described in fig18. transparent mode full transparent mode on scn interfaces (n=1, 2) if the micro controller outputs iso 7816 signals, a transparent mode allows to connect, cclk, cio, crst, cc4 and cc8 signals on outputs after an electrical level control. the at83c26 level shifters adapt the card signals to the smart card voltage selection. the cclk micro controller signal can be connected t o the a2/ck pins (see cksn[2:0]). cksn[2:0] bits allow to select standard or transpar ent configuration for the cclkn pin. a2/ck inputs always give the twi address at reset. if a2/ck input is tied to the host micro controller and its reset value is unknown, a general call on the twi bus allows to reset all the at83c26 devices and set its address after a2/ck input is fixed. vcc vpfdp vpfdm start standard deactivation start emergency deactivation cvcc crst cclk cio, cc4, cc8
30 7511d?scr?02/07 at83c26 figure 20. transparent mode description full transparent mode on scn interfaces (n= 3, 4, 5 ) the transparent mode with a2/ck is also available f or sc3, sc4 and sc5 interfaces without cc4 and cc8. figure 21. transparent mode description interrupts the int output is high by default. i nt is driven low by at least one of the following eve nt: ? insert1 or insert2 bits set (card insertion/extrac tion or bit set by software) ? vcard_intn (n=1,2,3,4,5) bits set (the dc/dc a or ldo2 to ldo5 output voltage has settled) ? vdcb_int bit set (the dc/dc b output voltage has s ettled) ? over-current detection on cvcc1 ? vcarderrn bit set (out of range voltage on cvccn o r bit set by software) (n=1,2,3,4,5) ? atrerrn bit set (no atr before the card clock coun ter overflows or bit set by software) (n=1,2,3,4,5) cclkn crstn cion i/o1 a2/ck smart card cclk cc4 micro controller cc8 cio aux1 aux2 cc4n cc8n at83c26 a1/rst crst cclkn crstn cion i/o2 a2/ck sim/sam cclk micro controller cio at83c26
31 7511d?scr?02/07 at83c26 several at83c26 devices can share the same interrup t pin and the micro controller can identify the interrupt sources by polling the interrupt bits of the at83c26 devices using twi commands. a twi read command of the interrupt bit correspondi ng to the it clears the bit. when all it bits are cleared, the int output becomes high. the itdis register contains 4 bits to control scn i nterrupts (n= 2,3,4,5). if itdisn bit is set, the flags are set but the int pin isn?t driven low if an interrupt event appears . table 4. interrupt bits description bit name register name mask on int pin remark insert1 insert2 vcard_int1 vcard_int2 vcard_int3 vcard_int4 vcard_int5 vdcb_int icarderr1 vcarderr1 vcarderr2 vcarderr3 vcarderr4 vcarderr5 atrerr1 atrerr2 atrerr3 atrerr4 atrerr5 sc1_cfg0 sc2_cfg0 sc1_status sc2_cfg0 sc3_cfg0 sc4_cfg0 sc5_cfg0 dcdcb sc1_cfg0 sc1_cfg0 sc2_cfg0 sc3_cfg0 sc4_cfg0 sc5_cfg0 sc1_cfg0 sc2_cfg0 sc3_cfg0 sc4_cfg0 sc5_cfg0 itdis2 itdis2 itdis3 itdis4 itdis5 itdis2 itdis3 itdis4 itdis5 itdis2 itdis3 itdis4 itdis5 smart card inserted/extracted in sc1 smart card inserted/extracted in sc2 vcard_ok1 is set vcard_ok2 is set vcard_ok3 is set vcard_ok4 is set vcard_ok5 is set vdcb_ok is set over current on dcdca. ouput voltage out of range on dcdca ouput voltage out of range on ldo2 ouput voltage out of range on ldo3. ouput voltage out of range on ldo4 ouput voltage out of range on ldo5 error on sc1 for atr reception in automatic mode error on sc2 for atr reception in automatic mode error on sc3 for atr reception in automatic mode error on sc4 for atr reception in automatic mode error on sc5 for atr reception in automatic mode
32 7511d?scr?02/07 at83c26 after the reading and the clear of the interrupt bi ts, several bits are used to control the status. table 5. status bits description the status for the icarderr1 and vcarderrn (n= 1 to 5) bits is controlled with vcard_okn bits. the status for the atrerrn (n= 1 to 5) is controlle d by reading of values in capture_msb and capture_lsb. slew rate control the at83c26 proposed a slew rate control on cion an d cclkn pins (n=1, 2, 3, 4, 5). the con- trol operates on rising and falling edges of cclkn and only on rising edge of cion. four modes are available: ? automatic mode: the slew rate depends on vcardn[1: 0] value. the slew rate value is optimized according to cvccn. ? mode 1, 2 , 3 (1.8v, 3v, 5v): the user can forced the slew rate if needed. for example if cvccn = 5v, the user can program 1.8v or 3v to spee d up the slew rate in case of long wire connection between at83c26 and smart cards. power down mode shutdowna bit and shutdownb bit must be set to acti vate power down mode on dcdca and dcdcb converters. if shutdowna = shutdownb = 1, the at83c26 internal regulator also enters in power down mode. the consumption is then about 30a. to exit from power down mode, twi commands are need ed to clear shutdowna and shutdownb. bit name register name remark cardin1 cardin2 vcard_ok1 vcard_ok2 vcard_ok3 vcard_ok4 vcard_ok5 vdcb_ok sc1_status sc1_status sc1_status sc2_cfg0 sc3_cfg0 sc4_cfg0 sc5_cfg0 dcdcb smart card presence in sc1 smart card presence in sc2 cvcc1 voltage in range programmed in vcard1[1:0] cvcc2 voltage in range programmed in vcard2[1:0] cvcc3 voltage in range programmed in vcard3[1:0] cvcc4 voltage in range programmed in vcard4[1:0] cvcc5 voltage in range programmed in vcard5[1:0] cvccb voltage in range programmed in vdcb[1:0]
33 7511d?scr?02/07 at83c26 write commands the write commands are: 1. general call reset: a general call followed by the value 06h has the sa me effect as a reset command. 2. reset: initialize all the logic and the twi interface as a fter a power-up or power-fail reset. if the interface is activated, an emergency de-activation sequence is also performed. this is a one-byte command. 3. write sc1_cfg0, sc1_cfg1, sc1_cfg2, sc1_cfg3, sc1 _cfg4: configure the device according to the last six bits in the sc1_cfg0 register and to the fol- lowing four bytes in sc1_cfg1, sc1_cfg2, sc1_cfg3 t hen sc1_cfg4 registers. this is a five bytes command. figure 22. command byte format for write sc1_cfg0 command 4. write timer_msb, timer_lsb: program the 16-bit automatic reset transition timer with the following two bytes. this is a three bytes command. 5. write sc1_interface: program the interface byte. this is a one-byte comm and. the msb of the command byte is fixed at 0. 6. write common config smart cards: io_select, interface_b, itdis: configuration of parameters for smart card interfac es. 7. write sc2 interface: sc2_cfg0, sc2_cfg1, sc2_cfg2 configuration of smart card interface 2. 8. write sc3 interface: sc3_cfg0, sc3_cfg2 configuration of sim/sam interface 3. 9. write sc4 interface: sc4_cfg0, sc4_cfg2 configuration of sim/sam interface 4. b7 b6 b5 b4 b3 b2 b1 1 x 0 x x x x sc1_cfg0 on 6 bits b0 x
34 7511d?scr?02/07 at83c26 10. write sc5 interface: sc5_cfg0, sc5_cfg2 configuration of sim/sam interface 5. 11. write dcdcb config: dcdcb, ldo configuration of dcdcb converter. 12. write slew_ctrl config: slew_ctrl_1, slew_ctrl_2 , slew_ctrl_3 configuration of slew rate for cclkn and cion (n = 1, 2, 3, 4, 5). table 6. write commands description address byte (see table 2) command byte data byte 1 data byte 2 data byte 3 data byte 4 [0] [1] [2] [3] [4] 1. general call reset 0000 0000 0000 0110 2. reset 0100 xx10 1111 1111 3. write config 0100 xx10 (10 + sc1_cfg0 6 bits) sc1_cfg1 sc1_cfg2 sc1_ cfg3 sc1_cfg4 4. write timer 0100 xx10 1111 1100 timer_msb timer_lsb 5. write interface 0100 xx10 (0+sc1_interface 7 bits) 6.write config sc on dcdcb 0100 xx10 1111 1000 io_select interface_b itdis 7. write sc2 interface 0100 xx10 1111 1001 sc2_cfg0 sc2_cfg1 sc2_cfg2 8. write sc3 interface 0100 xx10 1111 1010 sc3_cfg0 sc3_cfg2 9. write sc4 interface 0100 xx10 1111 1011 sc4_cfg0 sc4_cfg2 10. write sc5 interface 0100 xx10 1111 1101 sc5_cfg0 sc5_cfg2 11. write dcdcb config 0100 xx10 1111 1110 dcdcb ldo 12. write slew_ctrl config 0100 xx10 1111 0111 slew_ctrl_1 slew_ctrl_2 slew_ctrl_3
35 7511d?scr?02/07 at83c26 read command after a write command, even with a length of 0 byte , the next read operation is performed on the corresponding byte. the write command sets the ?rea d pointer?. after the reset, the ?read pointer? is on sc1 regis ters ffh is completing the transfer if the micro control ler attempts to read beyond the last byte. flags are only reseted after the corresponding byte read has been acknowledged by the master. figure 23. read command byte table 7. read commands description b7 b6 b5 b4 b3 b2 b1 0 0 1 0 x x 1 levels on reset b0 1 a2 a1 1. after reset or write command number 2, 3, 4 2. after write command number 6 3. after write command number 7 4. after write command number 8 5. after write command number 9 6. after write command number 10 7. after write command number 11 8. after write command number 12 [0] sc1_status statusb sc2_cfg0 sc3_cfg0 sc4_cfg0 sc5_cfg0 dc dcb slew_ctrl_1 [1] sc1_cfg0 io_select sc2_cfg1 sc3_cfg2 sc4_cfg2 sc5_cfg2 ld o slew_ctrl_2 [2] sc1_cfg1 interface_b sc2_cfg2 0xff 0xff 0xff 0xff slew_ctr l_3 [3] sc1_cfg2 itdis 0xff 0xff 0xff 0xff 0xff 0xff [4] sc1_cfg3 0xff 0xff 0xff 0xff 0xff 0xff 0xff [5] sc1_cfg4 0xff 0xff 0xff 0xff 0xff 0xff 0xff [6] sc1_interface 0xff 0xff 0xff 0xff 0xff 0xff 0xff [7] timer_msb 0xff 0xff 0xff 0xff 0xff 0xff 0xff [8] timer_lsb 0xff 0xff 0xff 0xff 0xff 0xff 0xff [9] capture_msb 0xff 0xff 0xff 0xff 0xff 0xff 0xff [10] capture_lsb 0xff 0xff 0xff 0xff 0xff 0xff 0xff [11] 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
36 7511d?scr?02/07 at83c26 registers summary the table below gives a quick view on at83c26 regis ters. table 8. smart card 1 interface registers table 9. smart card 2 interface registers table 10. sim/sam 3 interface registers table 11. sim/sam 4 interface registers table 12. sim/sam 5 interface registers 7 6 5 4 3 2 1 0 sc1_cfg0 1 0 atrerr1 insert1 icarderr1 vcarderr1 vcard11 vcard10 sc1_cfg1 x art1 shutdowna carddet1 pullup1 cds12 cds11 cds10 sc1_cfg2 0 dck2 dck1 dck0 x cks12 cks11 cks10 sc1_cfg3 x x x iccadja x x x x sc1_cfg4 x demboosta1 demboosta0 steprega int_pullup x x crst_sel1 sc1_interface 0 iodis1 ckstop1 cardrst1 cardc81 cardc41 cardck1 cardio1 sc1_status cc81 cc41 cardin1 vcard_ok1 x vcard_int1 crst1 cio1 7 6 5 4 3 2 1 0 sc2_cfg0 vcard_int2 vcard_ok2 atrerr2 insert2 x vcarderr2 vcard21 v card20 sc2_cfg1 x x sc2_full carddet2 pullup2 cds22 cds21 cds20 sc2_cfg2 art2 crst_sel2 cardrst2 cardck2 ckstop2 cks22 cks21 cks20 7 6 5 4 3 2 1 0 sc3_cfg0 vcard_int3 vcard_ok3 atrerr3 x x vcarderr3 vcard31 vcard30 sc3_cfg2 art3 x cardrst3 cardck3 ckstop3 ck32 cks31 cks30 7 6 5 4 3 2 1 0 sc4_cfg0 vcard_int4 vcard_ok4 atrerr4 x x vcarderr4 vcard41 vcard40 sc4_cfg2 art4 x cardrst4 cardck4 ckstop4 cks42 cks41 cks40 7 6 5 4 3 2 1 0 sc5_cfg0 vcard_int5 vcard_ok5 atrerr5 x x vcarderr5 vcard51 vcard50 sc5_cfg2 art5 x cardrst5 cardck5 ckstop5 cks52 cks51 cks50
37 7511d?scr?02/07 at83c26 table 13. common registers for sc1/sc2/sc3/sc4/sc5 table 14. common registers for sc2/sc3/sc4/sc5 table 15. dc/dc b registers table 16. slew control registers for cio and cclk pins 7 6 5 4 3 2 1 0 timer_msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 timer_lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 capture_msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 capture_lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 io_select x x x x iosel3 iosel2 iosel1 iosel0 7 6 5 4 3 2 1 0 interfaceb x cardc82 cardio5 cardio4 cardio3/ cardc42 cardio2 demboostb1 demboostb0 statusb x cardin2 cio5 cio4 crst3/ cc82 cio3/ cc42 crst2 cio2 itdis iodis5 iodis4 iodis3 iodis2 itdis5 itdis4 itdis3 itdis2 7 6 5 4 3 2 1 0 dcdcb shutdownb vdcb_int vdcb_ok 0 iccadjb stepregb vdcb1 vdcb0 ldo iplus5 iplus4 iplus3 iplus2 1 1 1 1 7 6 5 4 3 2 1 0 slew_ctrl_1 cclk2_slew_ctr l1 cclk2_slew_ct rl0 cio2_slew_ct rl1 cio2_slew_ct rl0 cclk1_slew_ct rl1 cclk1_slew_ct rl0 cio1_slew_ct rl1 cio1_slew_ctr l0 slew_ctrl_2 cclk4_slew_ctr l1 cclk4_slew_ct rl0 cio4_slew_ct rl1 cio4_slew_ct rl0 cclk3_slew_ct rl1 cclk3_slew_ct rl0 cio3_slew_ct rl1 cio3_slew_ctr l0 slew_ctrl_3 x x x x cclk5_slew_ct rl1 cclk5_slew_ct rl0 cio5_slew_ct rl1 cio5_slew_ctr l0
38 7511d?scr?02/07 at83c26 registers reset value = 0x 1000 0000 table 17. sc1_ cfg0(config byte 0 for sc1) 7 6 5 4 3 2 1 0 1 0 atrerr1 insert1 icarderr1 vcarderr1 vcard11 vcard10 bit number bit mnemonic description 7-6 1-0 these bits cannot be programmed and are read as 1-0. 5 atrerr1 answer to reset interrupt for sc1 this bit is set when the card clock counter overflo ws (no falling edge on cio1 is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose . 4 insert1 card insertion interrupt this bit is set when a card is inserted or extracte d: a change in cardin value filtered according to c ds[2-0]. it can be set by software for test purpose. this bit is cleared by hardware when this register is read. it cannot be cleared by software. 3 icarderr1 card over current interrupt this bit is set when an over current is detected on cvcc. it can be set by software for test purpose ( no card deactivation is performed). this bit is cleared by hardware when this register is read. it cannot be cleared by software. 2 vcarderr1 card out of range voltage interrupt this bit is set when the output voltage goes out of the voltage range specified by vcard field. it can be set by software for test purpose and deactivate the car d. this bit is cleared by hardware when this register is read. it cannot be cleared by software. 1-0 vcard1[1:0] card voltage selection vcard1[1:0] = 00: 0v vcard1[1:0] = 01: 1.8v vcard1[1:0] = 10: 3v vcard1[1:0] = 11: 5v vcard1[1:0] writing to 1.8v, 3v, 5v starts the dc/d c if a card is detected. vcard1[1:0] writing to 0 stops the dc/dc. no card deactivation is performed when the voltage is changed between 1.8v, 3v or 5v. the micro contro ller should deactivate the card before changing the volt age. table 18. sc1_cfg1 (config byte 1 for sc1 7 6 5 4 3 2 1 0 x art1 shutdowna carddet1 pullup1 cds12 cds11 cds10
39 7511d?scr?02/07 at83c26 reset value = 0x x000 1010 bit number bit mnemonic description 7 x 6 art1 automatic reset transition set this bit to have the crst1 pin changed accordin g to activation sequence. clear this bit to have the crst1 pin immediately fo llowing the value programmed in cardrst1. 5 shutdowna shutdown dc/dca set this bit to reduce the power consumption. an au tomatic de-activation sequence will be done. vcard[1:0] bits are reset. clear this bit to enable vcard1[1:0] selection. 4 carddet1 card presence detection polarity set this bit to indicate the card presence detector is closed when no card is inserted (cpres is low). clear this bit to indicate the card presence detect or is open when no card is inserted (cpres is high) . 3 pullup1 pull-up enable set this bit to enable the internal pull-up on the cpres pin. this allows to minimize the number of ex ternal components. clear this bit to disable the internal pull-up and minimize the power consumption when the card detect ion contact is on. then an external pull-up must be con nected to v cc (typically a 1 m resistor). 2-0 cds1[2:0] card detection filtering cpres1 is sampled by the master clock provided on c lk input. a change on cpres1 is detected after: cds1[2-0] = 0: no sample (1) cds1[2-0] = 1: 4 identical samples cds1[2-0] = 2: 8 identical samples (reset value) cds1[2-0] = 3: 16 identical samples cds1[2-0] = 4: 32 identical samples cds1[2-0] = 5: 64 identical samples cds1[2-0] = 6: 128 identical samples cds1[2-0] = 7: 256 identical samples note: 1. when cds[2-0] = 0, a card insertion (even if clk is stopped) puts a low level on int pin. this can be used to wake up the external micro controlle r and restart clk when a card is inserted in the at83c24. table 19. sc1_cfg2 (config byte 2 for sc1) 7 6 5 4 3 2 1 0 0 dck2 dck1 dck0 x cks12 cks11 cks10
40 7511d?scr?02/07 at83c26 reset value = 0x 0001 x000 notes: 1. when cks1 value is changed a special logic insures no glitch occurs on the cclk1 pin and actual configuration changes can be delayed by half a period to two periods of cclk1. 2. cclk1 must be stopped with ckstop1 bit before swi tching from cks1 = (0, 1, 2, 3, 6, 7) to cks1 = (4, 5) or vice versa. bit number bit mnemonic description 7 0 this bit must be always at 0. 6-4 dck[2:0] dck is the first level of prescaler factor. clk sig nal is divided by the prescaler value and outputs d cclk signal. dcclk is an input for cclk prescaler. dck[2:0] = 0: prescaler factor equals 1 dck[2:0] = 1: prescaler factor equals 2 dck[2:0] = 2: prescaler factor equals 4 dck[2:0] = 3: prescaler factor equals 6 dck[2:0] = 4: prescaler factor equals 8 dck[2:0] = 5: prescaler factor equals 10 dck[2:0] = 6: prescaler factor equals 12 dck[2:0] = 7: reserved dcclk is used for pad management and dectivation se quence. 3 x 2-0 cks1[2:0] card clock prescaler factor for cclk1. cks1 [2:0] = 0: cclk1 = clk (the maximum frequency on clk is 24 mhz) cks1 [2:0] = 1: cclk1 = dcclk cks1[2:0] = 2: cclk1 = dcclk / 2 cks1[2:0] = 3: cclk1 = dcclk / 4 cks 1[2:0] = 4: cclk1 = a2 cks1 [2:0] = 5: cclk1 = a2 / 2 cks1[2:0] = 6: cclk1 = clk / 2 cks1 [2:0] = 7: cclk1 = clk / 4 table 20. sc1_cfg3 (config byte 3 for sc1) 7 6 5 4 3 2 1 0 x x x iccadja x x x x bit number bit mnemonic description 7-5 x
41 7511d?scr?02/07 at83c26 reset value = 0x xxx0 xxxx 4 iccadja ci cc overflow adjust this bit controls the dc/dca sensitivity to any ove rflow current. set this bit to decrease the dc/dca sensitivity (ci cc_ovf is increased by about 20%). clear this bit to have a normal configuration. the reset value is 0. 3 x 2 x 1 x 0 x bit number bit mnemonic description table 21. sc1_cfg4 (config byte 4 for sc1) 7 6 5 4 3 2 1 0 x demboosta1 demboosta0 steprega int_pullup x x crst_sel1 bit number bit mnemonic description 7 x
42 7511d?scr?02/07 at83c26 reset value = 0x x000 0000 6-5 demboosta[1-0] dc/dc a maximum startup current drawn from power su pply 00: normal: 80 ma average 01: normal + 18% 10: normal + 18% (and boost on oscillator) 11: normal + 40% 4 steprega step regulator mode clear this bit to enable the automatic step-up conv erter (cvcc is stable even if vcc is not higher than cvcc). set this bit to permanently disable the step-up con verter (cvcc is stable only if vcc is sufficiently higher than cvcc). this bit must always be set if no external self is used 3 int_pullup internal pull-up set this bit to activate the internal pull-up (conn ected internally to vcc) on int pin. clear this bit to deactivate the internal pull-up. 2 x 1 x 0 crst_sel1 card reset selection set this bit to have the crst1 pin driven by hardwa re through the a1/rst pin. clear this bit to have the crst1 pin driven by soft ware through the cardrst bit. the reset value is 0. bit number bit mnemonic description table 22. sc1_interface (interface byte for sc1) 7 6 5 4 3 2 1 0 0 iodis1 ckstop1 cardrst1 cardc81 cardc41 cardck1 cardio1
43 7511d?scr?02/07 at83c26 reset value = 0x 0110 0000 bit number bit mnemonic description 7 0 this bit should not be set. 6 iodis1 card i/o isolation set this bit to drive the cio1, cc41, cc81 pins acc ording to cardio1, cardc41, cardc81 respectively. clear this bit to drive the cio1, cc41 and cc81 pin s connected to inputs according to iosel[3/0] bits. 5 ckstop1 card clock stop set this bit to stop cclk1 according to cardck1. th is can be used to set asynchronous cards in power- down mode (gsm) or to drive cclk1 by software. clear this bit to have cclk1 running according to c ks1. this can be used to activate asynchronous card s. note: when this bit is changed a special logic ensur es that no glitch occurs on the cclk1 pin and actual configuration changes can be delayed by half a period to two periods of cclk1. 4 cardrst1 card reset set this bit to enter a reset sequence according to art1 bit value. clear this bit to drive a low level on the crst1 pi n. 3 cardc81 card c8 set this bit to drive the cc81 pin high with the on -chip pull-up (according to iodis1 bit value). the pin can then be an input (read in sc1_status register). clear this bit to drive a low level on the cc81 pin (according to iodis1 bit value). 2 cardc41 card c4 set this bit to drive the cc41 pin high with the on -chip pull-up (according to iodis1 bit value). the pin can then be an input (read in sc1_status register). clear this bit to drive a low level on the cc41 pin (according to iodis1 bit value). 1 cardck1 card clock set this bit to set a high level on the cclk1 pin ( according to ckstop1 bit value). clear this bit to drive a low level on the cclk1 pi n. 0 cardio1 card i/o set this bit to drive the cio1 pin high with the on -chip pull-up (according to iodis1 bit value). the pin can then be an input (read in sc1_status register). clear this bit to drive a low level on the cio1 pin (according to iodis1 bit value). table 23. sc1_status (status byte for sc1) 7 6 5 4 3 2 1 0 cc81 cc41 cardin1 vcard_ok1 x vcard_int1 crst1 cio1 bit number bit mnemonic description 7 cc81 card cc8 this bit provides the actual level on the cc8 pin w hen read.
44 7511d?scr?02/07 at83c26 reset value = reset value depends on hardware confi guration 6 cc41 card cc4 this bit provides the actual level on the cc4 pin w hen read. 5 cardin1 card presence status this bit is set when a card is detected. it is cleared otherwise. 4 vcard_ok1 sc1 voltage status this bit is set by the dcdca when the output voltag e remains within the voltage range specified by vcard1[1:0] bits. it is cleared otherwise. 3 x 2 vcard_int1 sc1 smart card voltage interrupt this bit is set when vcard_ok1 bit is set. this bit is cleared when read by the micro controll er. 1 crst1 card rst this bit provides the actual level on the crst pin when read. 0 cio1 card i/o this bit provides the actual level on the cio pin w hen read. bit number bit mnemonic description table 24. sc2_cfg0 () 7 6 5 4 3 2 1 0 vcard_int 2 vcard_ok 2 atrerr2 insert2 x vcarderr2 vcard21 vcard20
45 7511d?scr?02/07 at83c26 reset value = 0x 0000 x000 bit number bit mnemonic description 7 vcard_int2 sc2 voltage interrupt this bit is set when vcard_ok2 bit is set. this bit is cleared when read by the micro controll er. 6 vcard_ok2 sc2 voltage status this bit is set by the ld02 when the output voltage remains within the voltage range specified by vcard2[1:0] bits. it is cleared otherwise. 5 atrerr2 answer to reset interrupt for sc2 this bit is set when the card clock counter overflo ws (no falling edge on cio2 is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose . 4 insert2 card insertion interrupt this bit is set when a card is inserted or extracte d in sc2 connector: a change in cardin2 value filte red according to cds2[2-0]. it can be set by software f or test purpose. this bit is cleared by hardware when this register is read. it cannot be cleared by software. 3 x 2 vcarderr2 interface 2 card out of range voltage interrupt this bit is set when the output voltage on cvcc n goes out of the voltage range specified by vcrdn f ield. it can be set by software for test purpose and deactiv ate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard2[1:0] interface 2 card voltage selection vcrd2[1:0] = 00: 0v vcrd2[1:0] = 01: 1.8v class c vcrd2[1:0] = 10: 3v class b vcrd2[1:0] = 11: 5v class a no card deactivation is performed when the voltage is changed. the micro controller should deactivate the card before changing the voltage and activating the card again. the reset value is 00.
46 7511d?scr?02/07 at83c26 reset value = 0x xx10 1010 table 25. sc2_cfg1 () 7 6 5 4 3 2 1 0 x x sc2_full carddet2 pullup2 cds22 cds21 cds20 bit number bit mnemonic description 7-6 x 5 sc2_full set this bit to activate full io interface on smart card 2: ? cio3/cc42 is cc42 and crst3/cc82 is cc82. ? interface 3 ldo is disabled. ? cardck3 is reset and ckstop3 to stop cclk on sc3. ? itdis3 is set to disable interrupts from sc3. cvcc2 and cvcc3 shall be connected externally and s c2_full must be set before activating the ldo. clear this bit only to use only cio on interface 2: ? cio3/cc42 is cio3 and crst3/cc82 is crst3. ? interface 3 can then be used independently to conn ect a sim/sam card. the reset value is 1. 4 carddet2 card presence detection polarity - interface 2 set this bit to indicate the card presence detector is closed when no card is inserted (cpres2 is low) . clear this bit to indicate the card presence detect or is open when no card is inserted (cpres2 is high ). the reset value is 0. 3 pullup2 pull-up enable set this bit to enable the internal pull-up on the cpres2 pin. this allows to minimize the number of e xternal components. clear this bit to disable the internal pull-up and minimize the power consumption when the card detect ion contact is on. then an external pull-up must be connected to v cc (typically a 1 m resistor). the reset value is 1. 2-0 cds2[2:0] card detection filtering - interface 2 cpres2 is sampled by the master clock provided on c lk input. a change on cpres2 is detected after: cds2[2-0] = 0: no sample (1) cds2[2-0] = 1: 4 identical samples cds2 [2-0] = 2: 8 identical samples (reset value) cds2[2-0] = 3: 16 identical samples cds2[2-0] = 4: 32 identical samples cds2[2-0] = 5: 64 identical samples cds2[2-0] = 6: 128 identical samples cds2[2-0] = 7: 256 identical samples note: 1. when cds2[2-0] = 0 and itdis2 = 0, a card in sertion (even if clk is stopped) puts a low level o n int pin. this can be used to wake up the external micr o controller and restart clk when a card is inserted in the at83c24.
47 7511d?scr?02/07 at83c26 reset value = 0x00001000 notes: 1. when cks2 value is changed a special logic insures no glitch occurs on the cclk2 pin and actual configuration changes can be delayed by half a period to two periods of cclk2. 2. cclk2 must be stopped with ckstop2 bit before swi tching from cks2 = (0, 1, 2, 3, 6, 7) to cks2 = (4, 5) or vice versa. table 26. sc2_cfg2 () 7 6 5 4 3 2 1 0 art2 crst_sel2 cardrst2 cardck2 ckstop2 cks22 cks21 cks20 bit number bit mnemonic description 7 art2 automatic reset transition set this bit to have the crst2 pin changed accordin g to activation sequence. clear this bit to have the crst2 pin immediately fo llowing the value programmed in cardrst2. 6 crst_sel2 card reset selection set this bit to have the crst2 pin driven by hardwa re through the a1/rst pin. clear this bit to have the crst pin driven by softw are through the cardrst bit. the reset value is 0. 5 cardrst2 card reset set this bit to enter a reset sequence according to art2 bit value. clear this bit to drive a low level on the crst2 pi n. 4 cardck2 card clock set this bit to set a high level on the cclk2 pin ( according to ckstop2 bit value). clear this bit to drive a low level on the cclk2 pi n. 3 ckstop2 card clock stop set this bit to stop cclk2 according to cardck2. th is can be used to set asynchronous cards in power- down mode (gsm) or to drive cclk2 by software. clear this bit to have cclk2 running according to c ks2. this can be used to activate asynchronous card s. note: when this bit is changed a special logic ensur es that no glitch occurs on the cclk2 pin and actua l configuration changes can be delayed by half a peri od to two periods of cclk2. 2-0 cks2[2:0] interface 2 card clock selection cks2 [2:0] = 0: cclk2 = clk (then the maximum frequ ency is 24 mhz) cks2 [3:0] = 1: cclk2 = dcclk cks2 [3:0] = 2: cclk2 = dcclk / 2 cks2 [3:0] = 3: cclk2 = dcclk / 4 cks2 [3:0] = 4: cclk2 = a2 cks2 [3:0] = 5: cclk2 = a2 / 2 cks2 [3:0] = 6: cclk2 = clk / 2 cks2 [3:0] = 7: cclk2 = clk / 4
48 7511d?scr?02/07 at83c26 reset value = 0x 000x 0000 table 27. sc3_cfg0() 7 6 5 4 3 2 1 0 vcard_int3 vcard_ok3 atrerr3 x x vcarderr3 vcard31 vcard30 bit number bit mnemonic description 7 vcard_int3 sc3 voltage interrupt this bit is set when vcard_ok3 bit is set. this bit is cleared when read by the micro controll er. 6 vcard_ok3 sc3 voltage status this bit is set by the ldo3 when the output voltage remains within the voltage range specified by vcard3[1:0] bits. it is cleared otherwise. 5 atrerr3 answer to reset interrupt for sc3 this bit is set when the card clock counter overflo ws (no falling edge on cio3 is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose . 4 x 3 x 2 vcarderr3 interface 3 card out of range voltage interrupt this bit is set when the output voltage on cvcc n goes out of the voltage range specified by vcrdn f ield. it can be set by software for test purpose and deactiv ate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard3[1:0] interface 3 card voltage selection vcrd3[1:0] = 00: 0v vcrd3[1:0] = 01: 1.8v class c vcrd3[1:0] = 10: 3v class b vcrd3[1:0] = 11: 5v class a no card deactivation is performed when the voltage is changed. the micro controller should deactivate the card before changing the voltage and activating the card again. the reset value is 00.
49 7511d?scr?02/07 at83c26 reset value = 0x 0x00 1000 notes: 1. when cks3 value is changed a special logic insures no glitch occurs on the cclk3 pin and actual configuration changes can be delayed by half a period to two periods of cclk3. 2. cclk3 must be stopped with ckstop3 bit before swi tching from cks3 = (0, 1, 2, 3, 6, 7) to cks3 = (4, 5) or vice versa. table 28. sc3_cfg2 () 7 6 5 4 3 2 1 0 art3 x cardrst3 cardck3 ckstop3 ck32 cks31 cks30 bit number bit mnemonic description 7 art3 automatic reset transition set this bit to have the crst3 pin changed accordin g to activation sequence. clear this bit to have the crst3 pin immediately fo llowing the value programmed in cardrst3. 6 x 5 cardrst3 card reset set this bit to enter a reset sequence according to art3 bit value. clear this bit to drive a low level on the crst3 pi n. this bit must be cleared to use aux2 pin for crst3 source. 4 cardck3 card clock set this bit to set a high level on the cclk3 pin ( according to ckstop3 bit value). clear this bit to drive a low level on the cclk3 pi n. 3 ckstop3 card clock stop set this bit to stop cclk3 according to cardck3. th is can be used to set asynchronous cards in power- down mode (gsm) or to drive cclk3 by software. clear this bit to have cclk3 running according to c ks3. this can be used to activate asynchronous card s. note: when this bit is changed a special logic ensur es that no glitch occurs on the cclk3 pin and actua l configuration changes can be delayed by half a peri od to two periods of cclk3. 2-0 cks3[2:0] interface 4card clock selection cks3 [2:0] = 0: cclk3 = clk (then the maximum frequ ency is 24 mhz) cks3 [3:0] = 1: cclk3 = dcclk cks3 [3:0] = 2: cclk3 = dcclk / 2 cks3 [3:0] = 3: cclk3 = dcclk / 4 cks3 [3:0] = 4: cclk3 = a2 cks3 [3:0] = 5: cclk3 = a2 / 2 cks3 [3:0] = 6: cclk3 = clk / 2 cks3 [3:0] = 7: cclk3 = clk / 4 the reset value is 0.
50 7511d?scr?02/07 at83c26 reset value = 0x 000x x000 table 29. sc4_cfg0() 7 6 5 4 3 2 1 0 vcard_int4 vcard_ok4 atrerr4 x x vcarderr4 vcard41 vcard40 bit number bit mnemonic description 7 vcard_int4 sc4 voltage interrupt this bit is set when vcard_ok4 bit is set. this bit is cleared when read by the micro controll er. 6 vcard_ok4 sc4 voltage status this bit is set by the ld04 when the output voltage remains within the voltage range specified by vcard4[1:0] bits. it is cleared otherwise. 5 atrerr4 answer to reset interrupt for sc4 this bit is set when the card clock counter overflo ws (no falling edge on cio4 is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose . 4 x 3 x 2 vcarderr4 interface 4 card out of range voltage interrupt this bit is set when the output voltage on cvcc n goes out of the voltage range specified by vcrdn f ield. it can be set by software for test purpose and deactiv ate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard4[1:0] interface 4 card voltage selection vcrd4[1:0] = 00: 0v vcrd4[1:0] = 01: 1.8v class c vcrd4[1:0] = 10: 3v class b vcrd4[1:0] = 11: 5v class a no card deactivation is performed when the voltage is changed. the micro controller should deactivate the card before changing the voltage and activating the card again. the reset value is 00.
51 7511d?scr?02/07 at83c26 reset value = 0x 0x00 1000 notes: 1. when cks4 value is changed a special logic insures no glitch occurs on the cclk4 pin and actual configuration changes can be delayed by half a period to two periods of cclk4. 2. cclk4 must be stopped with ckstop4 bit before swi tching from cks4 = (0, 1, 2, 3, 6, 7) to cks4 = (4, 5) or vice versa. table 30. sc4_cfg2 () 7 6 5 4 3 2 1 0 art4 x cardrst4 cardck4 ckstop4 cks42 cks41 cks40 bit number bit mnemonic description 7 art4 automatic reset transition set this bit to have the crst4 pin changed accordin g to activation sequence. clear this bit to have the crst4 pin immediately fo llowing the value programmed in cardrst4. 6 x 5 cardrst4 card reset set this bit to enter a reset sequence according to art4 bit value. clear this bit to drive a low level on the crst4 pi n. 4 cardck4 card clock set this bit to set a high level on the cclk4 pin ( according to ckstop4 bit value). clear this bit to drive a low level on the cclk4 pi n. 3 ckstop4 card clock stop set this bit to stop cclk4 according to cardck4. th is can be used to set asynchronous cards in power- down mode (gsm) or to drive cclk4 by software. clear this bit to have cclk4 running according to c ks4. this can be used to activate asynchronous card s. note: when this bit is changed a special logic ensur es that no glitch occurs on the cclk4 pin and actua l configuration changes can be delayed by half a peri od to two periods of cclk4. 2-0 cks4[2:0] interface 4card clock selection cks4 [2:0] = 0: cclk4 = clk (then the maximum frequ ency is 24 mhz) cks4 [3:0] = 1: cclk4 = dcclk cks4 [3:0] = 2: cclk4 = dcclk / 2 cks4 [3:0] = 3: cclk4 = dcclk / 4 cks4 [3:0] = 4: cclk4 = a2 cks4 [3:0] = 5: cclk4 = a2 / 2 cks4 [3:0] = 6: cclk4 = clk / 2 cks4 [3:0] = 7: cclk4 = clk / 4 the reset value is 0.
52 7511d?scr?02/07 at83c26 reset value = 0x 000x x000 table 31. sc5_cfg0() 7 6 5 4 3 2 1 0 vcard_int5 vcard_ok5 atrerr5 x x vcarderr5 vcard51 vcard50 bit number bit mnemonic description 7 vcard_int5 sc5 voltage interrupt this bit is set when vcard_ok5 bit is set. this bit is cleared when read by the micro controll er. 6 vcard_ok5 sc5 voltage status this bit is set by the ldo5 when the output voltage remains within the voltage range specified by vcard5[1:0] bits. it is cleared otherwise. 5 atrerr5 answer to reset interrupt for sc5 this bit is set when the card clock counter overflo ws (no falling edge on cio5 is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose . 4 x 3 x 2 vcarderr5 interface 5 card out of range voltage interrupt this bit is set when the output voltage on cvcc n goes out of the voltage range specified by vcrdn f ield. it can be set by software for test purpose and deactiv ate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard5[1:0] interface 5 card voltage selection vcrd5[1:0] = 00: 0v vcrd5[1:0] = 01: 1.8v class c vcrd5[1:0] = 10: 3v class b vcrd5[1:0] = 11: 5v class a no card deactivation is performed when the voltage is changed. the micro controller should deactivate the card before changing the voltage and activating the card again. the reset value is 00.
53 7511d?scr?02/07 at83c26 reset value = 0x 0x00 1000 notes: 1. when cks5 value is changed a special logic insures no glitch occurs on the cclk5 pin and actual configuration changes can be delayed by half a period to two periods of cclk5. 2. cclk5 must be stopped with ckstop5 bit before swi tching from cks5 = (0, 1, 2, 3, 6, 7) to cks5 = (4, 5) or vice versa. table 32. sc5_cfg2 () 7 6 5 4 3 2 1 0 art5 x cardrst5 cardck5 ckstop5 cks52 cks51 cks50 bit number bit mnemonic description 7 art5 automatic reset transition set this bit to have the crst5 pin changed accordin g to activation sequence. clear this bit to have the crst5 pin immediately fo llowing the value programmed in cardrst5. 6 x 5 cardrst5 card reset set this bit to enter a reset sequence according to art5 bit value. clear this bit to drive a low level on the crst5 pi n. 4 cardck5 card clock set this bit to set a high level on the cclk5 pin ( according to ckstop5 bit value). clear this bit to drive a low level on the cclk5 pi n. 3 ckstop5 card clock stop set this bit to stop cclk5 according to cardck5. th is can be used to set asynchronous cards in power- down mode (gsm) or to drive cclk5 by software. clear this bit to have cclk5 running according to c ks5. this can be used to activate asynchronous card s. note: when this bit is changed a special logic ensur es that no glitch occurs on the cclk5 pin and actua l configuration changes can be delayed by half a peri od to two periods of cclk5. 2-0 cks5[2:0] interface 5card clock selection cks5 [2:0] = 0: cclk5 = clk (then the maximum frequ ency is 24 mhz) cks5 [3:0] = 1: cclk5 = dcclk cks5 [3:0] = 2: cclk5 = dcclk / 2 cks5 [3:0] = 3: cclk5 = dcclk / 4 cks5 [3:0] = 4: cclk5= a2 cks5 [3:0] = 5: cclk5 = a2 / 2 cks5 [3:0] = 6: cclk5 = clk / 2 cks5 [3:0] = 7: cclk5 = clk / 4 the reset value is 0.
54 7511d?scr?02/07 at83c26 reset value = 0x 0000 0001 reset value = 0x 1001 0000 reset value = 0x 0000 0000 reset value = 0x 0000 0000 table 33. timer_msb (timer msb for sc1, sc2, sc3, sc4, sc5) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 timer msb (bits 15 to 8) table 34. timer_lsb (timer lsb for sc1, sc2, sc3, sc4, sc5) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 timer lsb (bits 7to 0) table 35. capture_msb (capture msb for sc1, sc2, sc3, sc4, sc 5) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 see section ?software activation fo r scn (n=1, 2, 3, 4, 5) interfaces and artn bit = 1 ?, page 25 table 36. capture_lsb (capture lsb for sc1, sc2, sc3, sc4, sc 5) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 see section ?software activation for scn (n=1, 2, 3 , 4, 5) interfaces and artn bit = 1?, page 25
55 7511d?scr?02/07 at83c26 reset value = 0x xxxx 1000 reset value for iosel[3:0]= 0x1000 table 37. io_select (selection byte for io) 7 6 5 4 3 2 1 0 x x x x iosel3 iosel2 iosel1 iosel0 bit number bit mnemonic description 7 x 6 x 5 x 4 x 3-0 iosel[3:0] io selection this field indicates the io routing between the hos t and the smart card interfaces when activated, seetable 38 and iodisn value (n=1, 2, 3, 4, 5). whe n no host io is routed to a smart card pin, this pi n is driven according to the interface register. see sec tion ?cio, cc4, cc8 controller?, page 15. table 38. io selection iosel[3:0] io1 io2 aux1 aux2 0000 cio1 - (1) - (1) - (1) 0001 cio2 - (1) - (1) - (1) - 0010 cio3 - (1) - (1) - (1) 0011 cio4 - (1) - (1) - (1) 0100 cio5 - (1) - (1) - (1) 0101 cio1 cio2 cc41 cio3/cc42 0110 cio1 cio2 cc41 cio4 0111 cio1 cio2 cc41 cio5 1000 cio1 cio2 cc41 cc81 1001 cio1 cio3 cc41 cc81 1010 cio1 cio4 cc41 cc81 1011 cio1 cio5 cc41 cc81 1100 cio1 cio5 cio3/cc42 cio4 1101 cio2 cio5 cio3/cc42 cio4 1110 cio2 cio4 cio3/cc42 crst3/cc82 1111 cio2 cio5 cio3/cc42 crst3/cc82
56 7511d?scr?02/07 at83c26 note: 1. if no input (io1, io2, aux1, aux2) is select ed for a scib pin (cion, cc4n cc8n), and if the smart card interface is started, the electrical lev el on the scib pin corresponds to the car- dion, cardc4n or cardc8n bit value. 2. for iosel[3:0] = 0xoe and iosel[3:0] = 0x0f, the cardrst3 bit must be set to connect aux2 to crst3/cc82 pin.
57 7511d?scr?02/07 at83c26 reset value = 0x x000 0000 table 39. interfaceb () 7 6 5 4 3 2 1 0 x cardc82 cardio5 cardio4 cardio3/car dc42 cardio2 demboostb1 demboostb0 bit number bit mnemonic description 7 x 6 cardc82 set this bit to drive the crst3/cc82 pin high with the on-chip pull-up (according to iodis2 bit value). the pin can then be an input (read in statu sb register). clear this bit to drive a low level on the cc82 pin (according to iodis2 bit value). 5 cardio5 set this bit to drive the cio5 pin high with the on -chip pull-up when isolated from the host (see ?itdis ()? on page 59.). the pin can then be an inp ut (read in statusb register). clear this bit to drive a low level on the cio5 pin when isolated from the host. 4 cardio4 set this bit to drive the cio4 pin high with the on -chip pull-up when isolated from the host (see ?itdis ()? on page 59.). the pin can then be an inp ut (read in statusb register). clear this bit to drive a low level on the cio4/c45 pin when isolated from the host. 3 cardio3/ cardc42 set this bit to drive the cio3/cc42 pin high with t he on-chip pull-up when isolated from the host (see ?itdis ()? on page 59.). the pin can then be a n input (read in statusb register). clear this bit to drive a low level on the cio3/cc4 2 pin when isolated from the host. this bit is cio3 when aux=0 or when aux=1 and ifn=2 , otherwise it is cc42. 2 cardio2 set this bit to drive the cio2 pin high with the on -chip pull-up when isolated from the host (see ?itdis ()? on page 59.). the pin can then be an inp ut (read in statusb register). clear this bit to drive a low level on the cio2 pin when isolated from the host. 1-0 demboostb[1-0] configuration for dc/dcb startup current. 00: normal: 80 ma average 01: normal + 18% 10: normal + 18% (and boost on oscillator) 11: normal + 40%
58 7511d?scr?02/07 at83c26 reset value = reset value depends on hardware confi guration table 40. statusb () - read only 7 6 5 4 3 2 1 0 x cardin2 cio5 cio4 crst3/ cc82 cio3/ cc42 crst2 cio2 bit number bit mnemonic description 7 x 6 cardin2 card presence status 2 this bit is set when a card is detected. it is cleared otherwise. 5 cio5 card cio5 this bit provides the actual level on the cio5 pin when read. 4 cio4 card cio4 this bit provides the actual level on the cio4 pin when read. 3 crst3/cc82 card crst3 this bit provides the actual level on the crst3 pin when read. 2 cio3/cc42 card cio3 this bit provides the actual level on the cio3 pin when read. 1 crst2 card crst2 this bit provides the actual level on the crst2 pin when read. 0 cio2 card cio2 this bit provides the actual level on the cio2 pin when read.
59 7511d?scr?02/07 at83c26 reset value = 0x 1111 0010 table 41. itdis () 7 6 5 4 3 2 1 0 iodis5 iodis4 iodis3 iodis2 itdis5 itdis4 itdis3 itdis2 bit number bit mnemonic description 7 iodis5 card i/o isolation set this bit to drive cio5 pin according to cardio5 . clear this bit to drive the cio5 pin connected to i nputs according to io_select registers. if iosel config doesn?t link an input to cio5, cio5 outputs cardio5 value. 6 iodis4 card i/o isolation set this bit to drive cio4 pin according to cardio4 . clear this bit to drive the cio4 pin connected to i nputs according to io_select registers. if iosel config doesn?t link an input to cio4, cio4 outputs cardio4 value. 5 iodis3 card i/o isolation set this bit to drive cio3 pin according to cardio3 . clear this bit to drive the cio3 pin connected to i nputs according to io_select registers. if iosel config doesn?t link an input to cio3, cio3 outputs cardio3 value. 4 iodis2 card i/o isolation set this bit to drive the cio2, cc42, cc82 pins acc ording to cardio2, cardc42, cardc82 respectively. clear this bit to drive the cio2, cc42 and cc82 pin s connected to inputs according to io_select regist er. if iosel config doesn?t link an input to cio2, cio2 outputs cardio2 value. 3 itdis5 interrupt disable of smart card interface 5 set this bit to disable interrupts from the interfa ce 5 (the flags are set but int pin is not driven). clear this bit to allow interrupts. 2 itdis4 interrupt disable of smart card interface 4 set this bit to disable interrupts from the interfa ce 4(the flags are set but int pin is not driven). clear this bit to allow interrupts. 1 itdis3 interrupt disable of smart card interface 3 set this bit to disable interrupts from the interfa ce 3 (the flags are set but int pin is not driven). clear this bit to allow interrupts. 0 itdis2 interrupt disable of smart card interface 2 set this bit to disable interrupts from the interfa ce 2(the flags are set but int pin is not driven). clear this bit to allow interrupts.
60 7511d?scr?02/07 at83c26 reset value = 0x 0000 0000 table 42. dcdcb (config interface b byte 2) 7 6 5 4 3 2 1 0 shutdownb vdcb_int vdcb_ok 0 iccadjb stepregb vdcb1 vdcb0 bit number bit mnemonic description 7 shutdownb shutdown dcdcb set this bit to reduce the power consumption. an au tomatic de-activation sequence will be done. clear this bit to enable vdcb. the reset value is 0. 6 vdcb_int dc/dc b voltage interrupt this bit is set when vcard_okb bit is set. this bit is cleared when read by the micro controll er. the reset value is 0. 5 vdcb_ok dc/dc b voltage status this bit is set by the dcdc when the output voltage remains within the voltage range specified by vdcb [1:0] bits. it is recommended to wait for this bit to be set before activating a card at the corresponding v oltage. it is cleared otherwise. the reset value is 0. 4 0 this bit must be always at 0. 3 iccadjb ci cc overflow adjust this bit controls the dc/dcb sensitivity to any ove rflow current. set this bit to decrease the dc/dcb sensitivity (ci cc_ovf is increased by about 20%). clear this bit to have a normal configuration. the reset value is 0. 2 stepregb dc/dc b step-up regulator mode set this bit to permanently disable the step-up con verter (cvcc is stable only if vcc is sufficiently higher than cvcc). this bit must always be set if no exter nal self is used. clear this bit to enable the automatic step-up conv erter (cvcc is stable even if vcc is not higher tha n cvcc). the reset value is 0. 1-0 vdcb[1:0] dc/dc b voltage selection vdcb[1:0] = 00: 0v vdcb[1:0] = 01: 2.2v (for class c) vdcb[1:0] = 10: 3.2v (for class b and c) vdcb[1:0] = 11: 5.2v (for class a, b and c) no card deactivation is performed when the voltage is changed. the voltage must be set higher than the voltage of all the active cards. if a class a card is deactivated and the remaining cards are in class b or c, vdcb can be reduced to 3.2v to reduce power consump tion. if a class b card is deactivated and the remaining cards are in class c, vdcb can be reduced to 2.2v to reduce power consumption.it is not rese t when cards are deactivated. it must be cleared by t he micro controller to stop dc/dc b (e.g. to reduce power consumption). the reset value is 00.
61 7511d?scr?02/07 at83c26 reset value = 0x 0000 1111 table 43. ldo 7 6 5 4 3 2 1 0 iplus5 iplus4 iplus3 iplus2 1 1 1 1 bit number bit mnemonic description 7 iplus5 if set, this bit increases the startup and o verflow current of ldo5 (+60%) 6 iplus4 if set, this bit increases the startup and o verflow current of ldo4 (+60%) 5 iplus3 if set, this bit increases the startup and o verflow current of ldo3 (+60%) 4 iplus2 if set, this bit increases the startup and o verflow current of ldo2 (+60%) 3 1 do not clear this bit. 2 1 do not clear this bit. 1 1 do not clear this bit. 0 1 do not clear this bit.
62 7511d?scr?02/07 at83c26 reset value = 0x 1111 1111 table 44. slew_ctrl_1(slew control for sc1 and sc2) 7 6 5 4 3 2 1 0 cclk2_slew_ct rl1 cclk2_slew_ct rl0 cio2_slew_ct rl1 cio2_slew_ct rl0 cclk1_slew_ct rl1 cclk1_slew_ctr l0 cio1_slew_ctr l1 cio1_slew_ct rl0 bit number bit mnemonic description 7-6 cclk2_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc2=5v) 0 1: mode 2 (optimum for cvcc2=3v) 1 0: mode 3 (optimum for cvcc2=1.8v) 1 1: automatic mode the reset value is 11. 5-4 cio2_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc2=5v) 0 1: mode 2 (optimum for cvcc2=3v) 1 0: mode 3 (optimum for cvcc2=1.8v) 1 1: automatic mode the reset value is 11. 3-2 cclk1_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc1=5v) 0 1: mode 2 (optimum for cvcc1=3v) 1 0: mode 3 (optimum for cvcc1=1.8v) 1 1: automatic mode the reset value is 11. 1-0 cio1_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc1=5v) 0 1: mode 2 (optimum for cvcc1=3v) 1 0: mode 3 (optimum for cvcc1=1.8v) 1 1: automatic mode the reset value is 11.
63 7511d?scr?02/07 at83c26 reset value = 0x 1111 1111 table 45. slew_ctrl_2 (slew control for sc3 and sc4) 7 6 5 4 3 2 1 0 cclk4_slew_ctr l1 cclk4_slew_ct rl0 cio4_slew_ct rl1 cio4_slew_ct rl0 cclk3_slew_ctr l1 cclk3_slew_ctrl 0 cio3_slew_ct rl1 cio3_slew_ctr l0 bit number bit mnemonic description 7-6 cclk4_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc4=5v) 0 1: mode 2 (optimum for cvcc4=3v) 1 0: mode 3 (optimum for cvcc4=1.8v) 1 1: automatic mode the reset value is 11. 5-4 cio4_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc4=5v) 0 1: mode 2 (optimum for cvcc4=3v) 1 0: mode 3 (optimum for cvcc4=1.8v) 1 1: automatic mode the reset value is 11. 3-2 cclk3_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc3=5v) 0 1: mode 2 (optimum for cvcc3=3v) 1 0: mode 3 (optimum for cvcc3=1.8v) 1 1: automatic mode the reset value is 11. 1-0 cio3_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc3=5v) 0 1: mode 2 (optimum for cvcc3=3v) 1 0: mode 3 (optimum for cvcc3=1.8v) 1 1: automatic mode the reset value is 11.
64 7511d?scr?02/07 at83c26 reset value = 0x xxxx 1111 table 46. slew_ctrl_3 (slew control for sc5) 7 6 5 4 3 2 1 0 x x x x cclk5_slew_ctr l1 cclk5_slew_ctr l0 cio5_slew_ctr l1 cio5_slew_ct rl0 bit number bit mnemonic description 7-4 x 3-2 cclk5_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc5=5v) 0 1: mode 2 (optimum for cvcc5=3v) 1 0: mode 3 (optimum for cvcc5=1.8v) 1 1: automatic mode the reset value is 11. 1-0 cio5_slew_ctrl[1-0] 0 0: mode 1 (optimum for cvcc5=5v) 0 1: mode 2 (optimum for cvcc5=3v) 1 0: mode 3 (optimum for cvcc5=1.8v) 1 1: automatic mode the reset value is 11.
65 7511d?scr?02/07 at83c26 electrical characteristics absolute maximum ratings * (**) exposed die attached pad must be soldered to g round thermal resistor is measured on multi-layer pcb wit h 0 m/s air flow. (***) including shortages between any groups of sma rt card pins. ac/dc parameters evcc connected to host power supply: from 2.5v to 5 .5v. t a = -40 c to +85 c; v ss = 0v; v cc = 3v to 5.5v. class a (5v) for smart card 1, 2, 3, 4, 5 supplied with cvcc (+/- 8%) class b (3v)for smart card 1, 2, 3, 4, 5 supplied w ith cvcc (+/- 8%) class c (1.8v) for smart card 1, 2, 3, 4, 5 supplie d with cvcc (+/- 8%) ambient temperature under bias: ................... .- 40 c to 85 c storage temperature: ............................... .... -65 c to +150 c voltage on vcc: ................................... ..... v ss -0.5v to +6.0v voltage on scib pins (***): ......... cvss -0.5v to cvcc + 0.5v voltage on host interface pins:.......vss -0.5v to evcc + 0.5v voltage on other pins: ...................... vss -0.5v to vcc + 0.5v max power dissipation: ............................ .................. 350mw thermal resistor of qfn package (**)............... .......24c/w thermal resistor of vqfp package................... ........67c/w *notice: stresses at or above those listed under ?ab solute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maxi- mum allowable die temperature and the thermal resistance of the package. table 47. core (vcc) symbol parameter min typ max unit test conditions v pfdp power fail high level threshold 2.46 2.59 2.75 v v pfdm power fail low level threshold 2.26 2.40 2.56 v hysteresis delta between (vpfdp - vpfdm) 100 190 300 mv t rise vcc rise time 1us 10s s t fall vcc fall time 100us 10s i cc operating operating current 0.25 * clk +12 ma dcdca, dcdcb and ldos on with load= 0 ma vcc = 5.5v i cc power down power down current 30 75 a shutdowna bit = 1 shutdownb bit = 1 vcc = 5.5v clk on chip oscillator 4 48 mhz
66 7511d?scr?02/07 at83c26 table 48. host interface (io1, io2, aux1, aux2, clk, a2/ck, a 1/rst, int ) symbol parameter min typ max unit test conditions v il input low-voltage 0.8 v v ih input high voltage 2.2 v v ol output low voltage 0.3 v i ol = -500a v oh output high voltage vcc - 0.7v v i oh = +30a table 49. host interface (scl, sda, r eset ) sym?bol parameter min typ max unit test conditions v il input low-voltage 0.8 v v ih input high voltage 2.2 v v ol output low voltage 0.3 v i ol = -3ma table 50. smart card 1 class a, 5v (cvcc1) symbol parameter min typ max unit test conditions cvcc smart card voltage 4.6 5 5.4 v load = 60ma vcc = 3v to 5.5v if stepreg = 0 vcc > 5.3v if stepreg = 1 ci cc _ovf card supply current overflow: iccadja = 0 (reset value) 90 ma ripple on cvcc 32 96 240 mv with low esr capacitance (0.1 ohms max) spikes on cvcc 0.5 v vcardok up vcardok high level threshold 5 v vcardok down vcardok low level threshold 4.64 v t vhl cvcc valid to 0.4v 100 500 s c l =10 f t vlh cvcc 0 to valid 1000 4000 s c l = 10 f table 51. smart card 1 class b, 3v (cvcc1) symbol parameter min typ max unit test conditions cvcc smart card voltage 2.76 3 3.24 v load = 60ma vcc = 3v to 5.5v if stepreg = 0 vcc > 3.3v if stepreg = 1
67 7511d?scr?02/07 at83c26 ci cc _ovf card supply current overflow: iccadja = 0 (reset value) 85 ma ripple on cvcc 32 56 176 mv with low esr capacitance (0.1 ohms max) spikes on cvcc 0.4 v vcardok up vcardok high level threshold 3 v vcardok down vcardok low level threshold 2.816 v t vhl cvcc valid to 0.4v 100 400 s c l =10 f t vlh cvcc 0 to valid 300 2000 s c l = 10 f table 51. smart card 1 class b, 3v (cvcc1) (continued) symbol parameter min typ max unit test conditions table 52. smart card 1 class c, 1.8v (cvcc1) symbol parameter min typ max unit test conditions cvcc smart card voltage 1.656 1.8 1.944 v load = 35ma ci cc _ovf card supply current overflow: iccadja = 0 (reset value) 65 ma ripple on cvcc 30 38 56 mv spikes on cvcc 0.05 v vcardok up vcardok high level threshold 1.8 v vcardok down vcardok low level threshold 1.718 v t vhl cvcc valid to 0.4v 30 80 400 s c l =10 f t vlh cvcc 0 to valid 220 2000 s c l = 10 f table 53. smart card 2 class a, 5v (cvcc2) symbol parameter min typ max unit test conditions cvcc smart card voltage 4.6 5 5.4 v load = 60ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 75 ma ripple on cvcc 20 90 143 mv spikes on cvcc v vcardok up vcardok high level threshold 5 v vcardok down vcardok low level threshold 4.646 v t vhl cvcc valid to 0.4v 150 500 s c l =2.2 f
68 7511d?scr?02/07 at83c26 t vlh cvcc 0 to valid 200 2000 s c l = 2.2 f table 53. smart card 2 class a, 5v (cvcc2) (continued) symbol parameter min typ max unit test conditions table 54. smart card 2 class b, 3v (cvcc2) symbol parameter min typ max unit test conditions cvcc smart card voltage 2.76 3 3.24 v load = 60ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 60 ma ripple on cvcc 29 88 164 mv spikes on cvcc v vcardok up vcardok high level threshold 3 v vcardok down vcardok low level threshold 2.825 v t vhl cvcc valid to 0.4v 100 500 s c l =2.2 f t vlh cvcc 0 to valid 100 1000 s c l = 2.2 f table 55. smart card 2 class c, 1.8v (cvcc2) symbol parameter min typ max unit test conditions cvcc smart card voltage 1.656 1.8 1.944 v load = 35ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 75 ma ripple on cvcc 29 86 158 mv spikes on cvcc v vcardok up vcardok high level threshold 1.8 v vcardok down vcardok low level threshold 1.651 v t vhl cvcc valid to 0.4v 70 500 s c l =2.2 f t vlh cvcc 0 to valid 80 1000 s c l = 2.2 f table 56. smart card 3, 4, 5 class a, 5v (cvcc3, cvcc4, cvcc5 ) symbol parameter min typ max unit test conditions cvcc smart card voltage 4.6 5 5.4 v load = 30ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 70 ma
69 7511d?scr?02/07 at83c26 ripple on cvcc 32 78 134 mv spikes on cvcc v vcardok up vcardok high level threshold 5 v vcardok down vcardok low level threshold 4.514 v t vhl cvcc valid to 0.4v 50 500 s c l =470nf t vlh cvcc 0 to valid 200 2000 s c l = 470nf table 56. smart card 3, 4, 5 class a, 5v (cvcc3, cvcc4, cvcc5 ) (continued) symbol parameter min typ max unit test conditions table 57. smart card 3, 4, 5 class b, 3v (cvcc3, cvcc4, cvcc5 ) symbol parameter min typ max unit test conditions cvcc smart card voltage 2.76 3 3.24 v load = 30ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 70 ma ripple on cvcc 32 82 175 mv spikes on cvcc v vcardok up vcardok high level threshold 3 v vcardok down vcardok low level threshold 2.791 v t vhl cvcc valid to 0.4v 40 500 s c l =470nf t vlh cvcc 0 to valid 100 2000 s c l = 470nf table 58. smart card 3, 4, 5 class c, 1.8v (cvcc3, cvcc4, cvc c5) symbol parameter min typ max unit test conditions cvcc smart card voltage 1.656 1.8 1.944 v load = 15ma ci cc _ovf card supply current overflow: iccadjb = 0 (reset value) 75 ma ripple on cvcc 32 84 178 mv spikes on cvcc v vcardok up vcardok high level threshold 1.8 v vcardok down vcardok low level threshold 1.65 v t vhl cvcc valid to 0.4v 30 500 s c l =470nf t vlh cvcc 0 to valid 100 2000 s c l = 470nf
70 7511d?scr?02/07 at83c26 table 59. smart card 1, 2, 3, 4, 5 clock (cclk1, cclk2, cclk3 , cclk4, cclk5) symbol parameter min typ max unit test conditions v ol output low voltage 0.3 v class a: i ol = -200a class b: i ol = -200a class c: i ol = -200a v oh output high voltage 0.8 cvcc v class a: i oh = 200a class b: i oh = 200a class c: i oh = 200a t r rise time (see tables 66 to 68) 16 ns c l = 30pf class a c l = 30pf class b c l = 30pf class c t f fall time (see tables 66 to 68) 16 ns c l = 30pf class a c l = 30pf class b c l = 30pf class c low level voltage stability (taking into account pcb design) -0.25 -0.25 -0.25 0.6 0.4 0.4 v class a class b class c high level voltage stability (taking into account pcb design) cvcc-0.5 cvcc+0.25 v cvcc= class a, class b or class c cclk smart card clock frequency 24 mhz table 60. smart card n i/os (cion, cc4n, cc8n, crstn) (n =1, 2, 3, 4, 5) symbol parameter min typ max unit test conditions v il input low-voltage -0.5 0.15 cvcc v v ih input high voltage 0.7 cvcc cvcc + 0.5 v v ol output low-voltage 0.3 v i ol = -1ma v oh output high voltage 0.8 cvcc v class a: i oh = 20a class b: i oh = 20a class c: i oh = 20a i il input low current 600 a i ih input high current -40 +40 a i os output short circuit current -15 +15 ma short to gnd or cvcc low level voltage stability (taking into account pcb design) -0.25 -0.25 -0.25 0.6 0.4 0.4 v class a class b class c high level voltage stability (taking into account pcb design) cvcc-0.5 cvcc+0.25 v cvcc= class a, class b or class c t r rise time (see tables 63 to 65) 100 ns c l = 30pf class a c l = 30pf class b c l = 30pf class c
71 7511d?scr?02/07 at83c26 t f fall time 100 ns c l = 30pf class a c l = 30pf class b c l = 30pf class c table 60. smart card n i/os (cion, cc4n, cc8n, crstn) (n =1, 2, 3, 4, 5) (continued) symbol parameter min typ max unit test conditions table 61. card presence (cpres1, cpres2) symbol parameter min typ max unit test conditions i ol1 cpres1 weak pull-up output current 3 10 25 a short to vss pullup1 = 1: internal pull-up active r cpres2 cpres2 weak pull-up output current 3 10 25 a short to vss pullup2 = 1: internal pull-up active table 62. dcdcb symbol parameter min typ max unit test conditions cvccb dcdcb output voltage 4.9 32 5.3 3.35 2.4 v load = 75ma load = 40ma load = 10ma ripple on cvccb 200 mv vcardok up vdcbok high level threshold 5.3 3.35 2.4 v class a class b class c vcardok down vdcbok low level threshold 4.9 3.1 2.1 v class a class b class c t vhl vdcb valid to 0 100 500 s t vlh vdcb 0 to valid 1000 4000 s table 63. slew rate on cion with cvccn= 5v (n=1, 2, 3, 4, 5), mode 1 symbol parameter min typ max unit test conditions t r/f rise time/ fall time with cion_slew_ctrl[1-0] = 00 (5v) or cion_slew_ctrl[1-0] = 11(mode auto) 40 ns t r rise time with cion_slew_ctrl[1-0] = 01 (3v) 20 ns t r rise time with cion_slew_ctrl[1-0] = 10 (1.8v) 8 ns
72 7511d?scr?02/07 at83c26 table 64. slew rate on cion with cvccn= 3v (n=1, 2, 3, 4, 5), mode 2 symbol parameter min typ max unit test conditions t r/f rise time/ fall time with cion_slew_ctrl[1-0] = 01 (3v) or cion_slew_ctrl[1-0] = 11(mode auto) 30 ns t r rise time with cion_slew_ctrl[1-0] = 10 (1.8v) 12 ns table 65. slew rate on cion with cvccn= 1.8v (n=1, 2, 3, 4, 5 ), mode 3 symbol parameter min typ max unit test conditions t r/f rise time/ fall time with cion_slew_ctrl[1-0] = 10 (1.8v) or cion_slew_ctrl[1-0] = 11(mode auto) 25 ns table 66. slew rate on cclkn with cvccn= 5v (n=1, 2, 3, 4, 5) , mode 1 symbol parameter min typ max unit test conditions t r/f rise time/ fall time with cclkn_slew_ctrl[1-0] = 00 (5v) or cclkn_slew_ctrl[1-0] = 11(mode auto) 12 ns t r/f rise time/ fall time with cclkn_slew_ctrl[1-0] = 01 (3v) 7 ns t r/f rise time/ fall time with cclkn_slew_ctrl[1-0] = 10 (1.8v) 2.7 ns table 67. slew rate on cclkn with cvccn= 3v (n=1, 2, 3, 4, 5) , mode 2 symbol parameter min typ max unit test conditions t r/f rise time/ fall time with cclkn_slew_ctrl[1-0] = 01 (3v) or cclkn_slew_ctrl[1-0] = 11(mode auto) 9 ns t r/f rise time/ fall time with cclkn_slew_ctrl[1-0] = 10 (1.8v) 4 ns table 68. slew rate on cclkn with cvccn= 1.8v (n=1, 2, 3, 4, 5), mode 3 symbol parameter min typ max unit test conditions t r rise time/ fall time with cclkn_slew_ctrl[1-0] = 10 (1.8v) or cclkn_slew_ctrl[1-0] = 11(mode auto) 8.5 ns
73 7511d?scr?02/07 at83c26 typical application 10f xtal1 xtal2 vss 4.7f vss 10h vss vss card 1 i nt clk vss crst1 cpres1 cio1, cc41, cc81 cclk1 cvcc1 lia cvss at83c26 scl sda io1,io2, aux1, aux2 v cc host twi int0 4 * px,y r eset 4 to 48 mhz lib cvccb 10f vss vss v cc card 2 crst2 cpres2 cio2, cc42, cc82 cclk2 card 3..5 crst3..5 cio3..5 cclk3..5 100nf 10h a2/ck a1/rst cclk crst0 smart card interface vcc cvcc3..5 3 * 470nf vss cvss vss 100nf vss 4.7h card 0 pres/int clk vss crst cpres cio, cc4, cc8 cclk li cvss at83c24 scl sda io, c4, c8 v cc r eset a2/ck a1/rst a0 vss dvcc 100nf 100nf vss crst1 vcc or vss cvcc1in cvccbin 10f cvss cvcc1 100nf cvss cvcc1in vss 2.2f vss 100nf px.y px.y bypass cvcc2 vss 2.2f evcc cvcc1 cvccb 100nf vss vss vcc 4.7k 4.7k 100k clk_out
74 7511d?scr?02/07 at83c26 ordering information samples part number supply voltage temperature range package p acking at83c26-pltul 3v to 5.5v industrial green mlf48 tray at83c26-plrul 3v to 5.5v industrial green mlf48 tape&r eel at83c26-rktul 3v to 5.5v industrial green vqfp48 tray at83c26-rkrul 3v to 5.5v industrial green vqfp48 tape& reel part number supply voltage temperature range package p acking at83c26-pltel 3v to 5.5v 25c mlf48 tray AT83C26-RKTEL 3v to 5.5v 25c vqfp48 tray
75 7511d?scr?02/07 at83c26 package drawings vqfp48
76 7511d?scr?02/07 at83c26 qfn48
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